View C8051F351_5057362.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8 k isp flash mcu family c8051f350/1/2/3 rev. 1.0 4/05 copyright ? 2005 by silicon laboratories c8051f35x analog peripherals - 24 or 16-bit adc no missing codes 0.0015% nonlinearity programmable conversion rates up to 1 ksps 8-input multiplexer 1x to 128x pga built-in temperature sensor - two 8-bit current output dacs - comparator programmable hysteresis and response time configurable as interrupt or reset source low current (0.4 a) on-chip debug - on-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) - provides breakpoints, single stepping, inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets - low cost, complete development kit supply voltage 2.7 to 3.6 v - typical operating current:5.8 ma @ 25 mhz; 11 a @ 32 khz - typical stop mode current:0.1 a temperature range: ?40 to +85 c high speed 8051 c core - pipelined instruction archit ecture; executes 70% of instructions in 1 or 2 system clocks - up to 50 mips throughput - expanded interrupt handler memory - 768 bytes (256 + 512) on-chip ram - 8k bytes flash; in-system programmable in 512- byte sectors digital peripherals - 17 port i/o; all 5 v tolerant with high sink current - enhanced uart, smbus?, and spi? serial ports - four general purpose 16-bit counter/timers - 16-bit programmable count er array (pca) with three capture/compare modules - real time clock mode using pca or timer and exter - nal clock source clock sources - internal oscillator: 24.5 mhz with 2% accuracy supports uart operation - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - clock multiplier to achieve 50 mhz internal clock - can switch between cl ock sources on-the-fly 28-pin qfn or 32-pin lqfp package - 5 x 5 mm pcb footprint with 28-qfn analog peripherals 24/16-bit adc 8kb isp flash 768 b sram por debug circuitry flexible interrupts 8051 cpu (50 mips) temp sensor digital i/o 24.5 mhz precision internal oscillator with clock multiplier high-speed controller core a m u x crossbar voltage comparator + - wdt uart smbus pca timer 0 timer 1 timer 2 timer 3 port 0 spi 8-bit idac port 1 p2.0 8-bit idac
c8051f350/1/2/3 2 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 3 table of contents 1. system overview............ ................ ................ ................. .............. .............. ........... 17 1.1. cip-51? microcontroller......... ................ ................ ................. .............. ........... 21 1.1.1. fully 8051 compatible inst ruction set.......... ................. ................ ........... 21 1.1.2. improved throughput ............ .............. .............. .............. .............. ........... 21 1.1.3. additional features .......... ................ ................. .............. .............. ........... 21 1.2. on-chip debug circuitr y.................... ................. ................ ................. ............. 22 1.3. on-chip memory......... ................ ................. .............. .............. .............. ........... 23 1.4. 24 or 16-bit analog to digita l converter (adc0) .............. ............ ........... ......... 24 1.5. two 8-bit current-mode dacs.... ................. .............. .............. .............. ........... 25 1.6. programmable comparator ...... ................ ................. .............. .............. ........... 26 1.7. serial ports ............ ................. ................ ................ ................. .............. ........... 26 1.8. port input/output....... ................ ................ ................. .............. .............. ........... 27 1.9. programmable counter array ... ................ ................. .............. .............. ........... 28 2. absolute maximum ratings ........ ................ ................ ................. .............. ........... 29 3. global dc electrical characteristi cs ...................... ................ ................. ............. 30 4. pinout and package definitions..... ............... ................. .............. .............. ........... 31 5. 24 or 16-bit analog to digital converter (adc0) ..... ................. ................ ........... 41 5.1. configuration............. ................ ................ ................. .............. .............. ........... 42 5.1.1. voltage reference selectio n................. .............. .............. .............. ......... 42 5.1.2. analog inputs .......... .............. .............. .............. .............. .............. ........... 42 5.1.2.1. programmable gain ampl ifier............. ................ ................. ............. 42 5.1.2.2. input buffers .... .............. .............. .............. .............. .............. ........... 42 5.1.3. modulator clock ............... ................ ................. .............. .............. ........... 43 5.1.4. decimation ratio ............ ................ ................ ................. .............. ........... 43 5.2. calibrating the adc ............. ................. ................ ................. ................ ........... 44 5.2.1. internal calibration ......... ................ ................ ................. .............. ........... 44 5.2.2. system calibration ......... ................ ................ ................. .............. ........... 44 5.2.3. calibration coefficient st orage............ .............. .............. .............. ........... 44 5.3. performing conversions .. .............. .............. .............. .............. .............. ........... 46 5.3.1. single conversions .......... ................ ................. .............. .............. ........... 46 5.3.2. continuous conversions ....... .............. .............. .............. .............. ........... 46 5.3.3. adc output .......... ................. .............. .............. .............. .............. ........... 46 5.3.4. error conditions ............... ................ ................. .............. .............. ........... 47 5.4. offset dac............. ................. ................ ................ ................. .............. ........... 47 5.5. burnout current sources ........ ................ ................ ................. .............. ........... 47 5.6. analog multiplexer ...... ................ ................. .............. .............. .............. ........... 59 6. 8-bit current mode dacs (ida0 and ida1)..... .............. .............. .............. ........... 67 6.1. idac output scheduling......... ................ ................ ................. .............. ........... 68 6.1.1. update output on-demand .. .............. .............. .............. .............. ........... 68 6.1.2. update output based on timer overflow ............. ............... ........... ......... 68 6.1.3. update output based on cnvstr edge................... ................. ............. 68 6.2. idac output mapping.......... ................. ................ ................. ................ ........... 68 6.3. idac external pin connections ................ ................. .............. .............. ........... 71
c8051f350/1/2/3 4 rev. 1.0 7. voltage reference .......... ................ ................ ................. .............. .............. ........... 73 8. temperature sensor....... ................ ................ ................. .............. .............. ........... 77 9. comparator0 ................ ................. ................ ................ ................. .............. ........... 79 9.1. comparator0 inputs and outputs ................. .............. .............. .............. ........... 83 10. cip-51 microcontroller .............. ................. ................ ................. ................ ........... 87 10.1.instruction set........... ................ ................ ................. .............. .............. ........... 89 10.1.1.instruction and cpu timing .. .............. .............. .............. .............. ........... 89 10.1.2.movx instruction and pr ogram memory .......... .............. .............. ........... 89 10.2.register descriptions .......... ................. ................ ................. ................ ........... 93 10.3.power management modes........ ................. .............. .............. .............. ........... 96 10.3.1.idle mode ........... ................ ................. .............. .............. .............. ........... 96 10.3.2.stop mode............ ................. .............. .............. .............. .............. ........... 96 11. memory organization and sfrs .. ............... ................ ................. .............. ........... 99 11.1.program memory........ ................ ................. .............. .............. .............. ........... 99 11.2.data memory ............ ................ ................ ................. .............. .............. ......... 100 11.3.general purpose registers ...... ................ ................. .............. .............. ......... 100 11.4.bit addressable locations ...... ................ ................ ................. .............. ......... 100 11.5.stack ............... ................ ................. ................ ................. ................ ......... 100 11.6.special function registers..... ................ ................ ................. .............. ......... 101 12. interrupt handler ............ ................ ................ ................. .............. .............. ......... 105 12.1.mcu interrupt source s and vectors.............. .............. .............. .............. ....... 105 12.2.interrupt priorities ..... ................ ................ ................. .............. .............. ......... 105 12.3.interrupt latency....... ................ ................ ................. .............. .............. ......... 105 12.4.interrupt register de scriptions ............. ................ ................. ................ ......... 107 12.5.external interrupts .... ................ ................ ................. .............. .............. ......... 111 13. prefetch engine ........... ................. ................ ................ ................. .............. ......... 113 14. reset sources.......... ................ ................ ................. ................ ................. ........... 115 14.1.power-on reset ....... ................ ................ ................. .............. .............. ......... 116 14.2.power-fail reset / vd d monitor ................. .............. .............. .............. ......... 117 14.3.external reset .......... ................ ................ ................. .............. .............. ......... 118 14.4.missing clock detector reset ... ............... ................. .............. .............. ......... 118 14.5.comparator0 reset ............. ................. ................ ................. ................ ......... 118 14.6.pca watchdog timer reset ..... ............... ................. .............. .............. ......... 118 14.7.flash error reset ..... ................ ................ ................. .............. .............. ......... 118 14.8.software reset ......... ................ ................ ................. .............. .............. ......... 118 15. flash memory ................. ................ ................ ................. .............. .............. ......... 121 15.1.programming the flash memory ................ .............. .............. .............. ......... 121 15.1.1.flash lock and key functi ons ................ .............. ............... ........... ....... 121 15.1.2.flash erase procedure ...... ................. .............. .............. .............. ......... 121 15.1.3.flash write procedure ..... ................ ................. .............. .............. ......... 122 15.2.non-volatile data storage ... ................. ................ ................. ................ ......... 123 15.3.security options ....... ................ ................ ................. .............. .............. ......... 123 16. external ram ............... ................. ................ ................ ................. .............. ......... 127 17. oscillators ................ ................ ................ ................. ................ ................. ........... 129 17.1.programmable internal oscilla tor .................... .............. ............... ........... ....... 129
c8051f350/1/2/3 rev. 1.0 5 17.2.external oscillator drive circuit................ ................. .............. .............. ......... 131 17.2.1.clocking timers direct ly through the exte rnal oscillator.... ........... ....... 131 17.2.2.external crystal example. ................ ................. .............. .............. ......... 131 17.2.3.external rc example....... ................ ................. .............. .............. ......... 133 17.2.4.external capacitor exampl e................ .............. .............. .............. ......... 133 17.3.clock multiplier ......... ................ ................ ................. .............. .............. ......... 135 17.4.system clock selectio n................. .............. .............. .............. .............. ......... 136 18. port input/output............ ................ ................ ................. .............. .............. ......... 137 18.1.priority crossbar decoder ... ................. ................ ................. ................ ......... 139 18.2.port i/o initialization ........ .............. .............. .............. .............. .............. ......... 141 18.3.general purpose port i/o .... ................. ................ ................. ................ ......... 144 19. smbus ................. ................ ................. .............. .............. .............. .............. ......... 151 19.1.supporting documents ............. ................ ................. .............. .............. ......... 152 19.2.smbus configuration... ............... ................. .............. .............. .............. ......... 152 19.3.smbus operation ....... ................ ................. .............. .............. .............. ......... 152 19.3.1.arbitration......... ................ ................ ................. .............. .............. ......... 153 19.3.2.clock low extension........ ................ ................. .............. .............. ......... 154 19.3.3.scl low timeout.... .............. .............. .............. .............. .............. ......... 154 19.3.4.scl high (smbus free) ti meout .............. ................ ................. ........... 154 19.4.using the smbus........ ................ ................. .............. .............. .............. ......... 155 19.4.1.smbus configuration regist er................ .............. ............... ........... ....... 156 19.4.2.smb0cn control register . ................. .............. .............. .............. ......... 159 19.4.3.data register ....... ................. .............. .............. .............. .............. ......... 162 19.5.smbus transfer modes... .............. .............. .............. .............. .............. ......... 163 19.5.1.master transmitter mode .. ............... ................. .............. .............. ......... 163 19.5.2.master receiver mode .............. ................. ................ ................. ........... 164 19.5.3.slave receiver mode ....... ................ ................. .............. .............. ......... 165 19.5.4.slave transmitter mode .... ............... ................. .............. .............. ......... 166 19.6.smbus status decoding ................ .............. .............. .............. .............. ......... 167 20. uart0................ ................ ................ ................. .............. .............. .............. ......... 171 20.1.enhanced baud rate g eneration.................. .............. .............. .............. ....... 172 20.2.operational modes ....... ................. .............. .............. .............. .............. ......... 173 20.2.1.8-bit uart ........... ................. .............. .............. .............. .............. ......... 173 20.2.2.9-bit uart ........... ................. .............. .............. .............. .............. ......... 174 20.3.multiprocessor communications ... .............. .............. .............. .............. ......... 174 21. serial peripheral interf ace (spi0) .............. ................ ................. ................ ......... 181 21.1.signal descriptions....... ................. .............. .............. .............. .............. ......... 182 21.1.1.master out, slave in (mos i)...................... ................ ................. ........... 182 21.1.2.master in, slave out (miso)............... .............. .............. .............. ......... 182 21.1.3.serial clock (sck) ........... ................ ................. .............. .............. ......... 182 21.1.4.slave select (nss) .......... ................ ................. .............. .............. ......... 182 21.2.spi0 master mode operation . ................ ................ ................. .............. ......... 183 21.3.spi0 slave mode operation ..... ................ ................. .............. .............. ......... 185 21.4.spi0 interrupt sources ........ ................. ................ ................. ................ ......... 185 21.5.serial clock timing... ................ ................ ................. .............. .............. ......... 186
c8051f350/1/2/3 6 rev. 1.0 21.6.spi special function registers . ............... ................. .............. .............. ......... 186 22. timers................ ................ ................ .............. .............. ............... .............. ........... 19 5 22.1.timer 0 and ti mer 1 ............... ................ ................ ................. .............. ......... 195 22.1.1.mode 0: 13-bit counter/timer ................. .............. ............... ........... ....... 195 22.1.2.mode 1: 16-bit counter/timer ................. .............. ............... ........... ....... 196 22.1.3.mode 2: 8-bit counter/tim er with auto-reload.......... ................. ........... 197 22.1.4.mode 3: two 8-bit counter /timers (timer 0 only)..... ................. ........... 198 22.2.timer 2 ............. ................ ................ ................. ................ ................. ........... 203 22.2.1.16-bit timer with auto-rel oad............... .............. .............. .............. ....... 203 22.2.2.8-bit timers with auto-rel oad............... .............. .............. .............. ....... 204 22.3.timer 3 ............. ................ ................ ................. ................ ................. ........... 207 22.3.1.16-bit timer with auto-rel oad............... .............. .............. .............. ....... 207 22.3.2.8-bit timers with auto-rel oad............... .............. .............. .............. ....... 208 23. programmable counter array ....... ................ ................. .............. .............. ......... 211 23.1.pca counter/timer ............. ................. ................ ................. ................ ......... 212 23.2.capture/compare modules ...... ................ ................. .............. .............. ......... 213 23.2.1.edge-triggered captur e mode................. .............. ............... ........... ....... 214 23.2.2.software timer (compare) mode................. ................. ................ ......... 215 23.2.3.high speed output mode............. ................ ................. ................ ......... 216 23.2.4.frequency output mode ....... .............. .............. .............. .............. ......... 217 23.2.5.8-bit pulse width modulato r mode............... ................. ................ ......... 218 23.2.6.16-bit pulse width modulat or mode............. ................. ................ ......... 219 23.3.watchdog timer mode .... .............. .............. .............. .............. .............. ......... 220 23.3.1.watchdog timer operation ... .............. .............. .............. .............. ......... 220 23.3.2.watchdog timer usage ........ .............. .............. .............. .............. ......... 221 23.4.register descriptions for pca. ............... ................ ................. .............. ......... 222 24. c2 interface ................ ................ ................. ................ ................. ................ ......... 227 24.1.c2 interface registers......... ................. ................ ................. ................ ......... 227 24.2.c2 pin sharing ......... ................ ................ ................. .............. .............. ......... 229
c8051f350/1/2/3 rev. 1.0 7 list of figures 1. system overview figure 1.1. c8051f350 block diagr am ...................... ................ ................. ............. 19 figure 1.2. C8051F351 block diagr am ...................... ................ ................. ............. 19 figure 1.3. c8051f352 block diagr am ...................... ................ ................. ............. 20 figure 1.4. c8051f353 block diagr am ...................... ................ ................. ............. 20 figure 1.5. development/in-syst em debug diagram................. ................. ............. 22 figure 1.6. memory map ........... ................ ................. ................ ................. ............. 23 figure 1.7. adc0 block diagram ... ................ ................ ................. .............. ........... 24 figure 1.8. idac block diagram . ................. ................ ................. ................ ........... 25 figure 1.9. comparator0 block di agram.................... ................ ................. ............. 26 figure 1.10. port i/o functional block diagram ................ .............. .............. ........... 27 figure 1.11. pca block diagram.... ................ ................ ................. .............. ........... 28 2. absolute maximum ratings 3. global dc electrical characteristics 4. pinout and package definitions figure 4.1. lqfp-32 pi nout diagram (top view) ............... .............. .............. ......... 34 figure 4.2. qfn-28 pinout diagr am (top view) .......... ................. ................ ........... 35 figure 4.3. lqfp-32 pa ckage diagram ................ .............. .............. .............. ......... 36 figure 4.4. qfn-28 package drawin g ................ .............. .............. .............. ........... 37 figure 4.5. typical qfn-28 landi ng diagram.............. ................. ................ ........... 38 figure 4.6. typical qfn-28 sol der paste diagram...... ................. ................ ........... 39 5. 24 or 16-bit analog to digital converter (adc0) figure 5.1. adc0 block diagram ... ................ ................ ................. .............. ........... 41 figure 5.2. adc0 buffer control ............. .............. .............. .............. .............. ......... 43 figure 5.3. adc0 offset calibration register coding ....... .............. .............. ........... 45 figure 5.4. adc0 gain calibrat ion register coding .. ................ ................. ............. 45 figure 5.5. adc0 multiplexer c onnections ................ ................ ................. ............. 59 6. 8-bit current mode dacs (ida0 and ida1) figure 6.1. idac functional bl ock diagram............ .............. ............... ........... ......... 67 figure 6.2. idac data word ma pping................. .............. .............. .............. ........... 68 figure 6.3. idac pin c onnections ............... ................ ................. ................ ........... 71 7. voltage reference figure 7.1. reference circuitry block diagram .......... ................ ................. ............. 73 8. temperature sensor figure 8.1. temperature sensor block diagram........ ................ ................. ............. 77 figure 8.2. single channel trans fer function............ ................ ................. ............. 78 figure 8.3. differential transfer function................ .............. ............... ........... ......... 78 9. comparator0 figure 9.1. comparator0 functi onal block diagram .... ................. ................ ........... 79 figure 9.2. comparator hysteres is plot ........... ................. .............. .............. ........... 80 figure 9.3. comparator pin co nnections ............ .............. .............. .............. ........... 83 10. cip-51 microcontroller figure 10.1. cip-51 block diagram.............. ................ ................. ................ ........... 87
c8051f350/1/2/3 8 rev. 1.0 11. memory organization and sfrs figure 11.1. memory map ........... ................. ................ ................. ................ ........... 99 12. interrupt handler 13. prefetch engine 14. reset sources figure 14.1. rese t sources.............. ................ ................. .............. .............. ......... 115 figure 14.2. power-on and vdd monitor reset timing ....... ............... ........... ....... 116 15. flash memory figure 15.1. flash memory map.. ................. ................ ................. ................ ......... 123 16. external ram 17. oscillators figure 17.1. oscillator diagram............... .............. .............. .............. .............. ....... 129 figure 17.2. 32.768 khz external crystal example...... ................. ................ ......... 132 18. port input/output figure 18.1. port i/o functional block diagram ................ .............. .............. ......... 137 figure 18.2. port i/o ce ll block diagram ............ .............. .............. .............. ......... 138 figure 18.3. crossbar priority decoder with no pins sk ipped ............... ................ 139 figure 18.4. crossbar priority decoder with crystal pins skipped .......... .............. 140 19. smbus figure 19.1. smbus block diagram ............. ................ ................. ................ ......... 151 figure 19.2. typical smbu s configuration .......... .............. .............. .............. ......... 152 figure 19.3. smbus transac tion ............. .............. .............. .............. .............. ....... 153 figure 19.4. typical sm bus scl generation........ .............. .............. .............. ....... 157 figure 19.5. typical ma ster transmitter sequence............. .............. .............. ....... 163 figure 19.6. typical ma ster receiver sequence................. .............. .............. ....... 164 figure 19.7. typical slave rece iver sequence............ ................. ................ ......... 165 figure 19.8. typical slave trans mitter sequence........ ................. ................ ......... 166 20. uart0 figure 20.1. uart0 block diagram ............. ................ ................. ................ ......... 171 figure 20.2. uart0 baud rate logic ............ ................ ................. .............. ......... 172 figure 20.3. uart interconnect di agram ............. .............. .............. .............. ....... 173 figure 20.4. 8-bit uart timing diagram............ .............. .............. .............. ......... 173 figure 20.5. 9-bit uart timing diagram............ .............. .............. .............. ......... 174 figure 20.6. uart multi-proc essor mode interconne ct diagram .......... ................ 175 21. serial periphera l interface (spi0) figure 21.1. spi bl ock diagram ............ .............. .............. .............. .............. ......... 181 figure 21.2. multiple -master mode connection diagram ...... ............... ........... ....... 184 figure 21.3. 3-wire single master and sl ave mode connection di agram ............. 184 figure 21.4. 4-wire single master and sl ave mode connection di agram ............. 184 figure 21.5. data/clock timing relationship ...... .............. .............. .............. ......... 186 figure 21.6. spi ma ster timing (ckpha = 0).. ................. .............. .............. ......... 191 figure 21.7. spi ma ster timing (ckpha = 1).. ................. .............. .............. ......... 191 figure 21.8. spi sl ave timing (ckpha = 0)....... .............. .............. .............. ......... 192 figure 21.9. spi sl ave timing (ckpha = 1)....... .............. .............. .............. ......... 192
c8051f350/1/2/3 rev. 1.0 9 22. timers figure 22.1. t0 mode 0 bl ock diagram............... .............. .............. .............. ......... 196 figure 22.2. t0 mode 2 bl ock diagram............... .............. .............. .............. ......... 197 figure 22.3. t0 mode 3 bl ock diagram............... .............. .............. .............. ......... 198 figure 22.4. timer 2 16- bit mode block diagram .. ............. .............. .............. ....... 203 figure 22.5. timer 2 8- bit mode block diagram .. ................. ............... ........... ....... 204 figure 22.6. timer 3 16- bit mode block diagram .. ............. .............. .............. ....... 207 figure 22.7. timer 3 8- bit mode block diagram .. ................. ............... ........... ....... 208 23. programmable counter array figure 23.1. pca block diagram.... ................ ................ ................. .............. ......... 211 figure 23.2. pca counter /timer block diagram.... ............. .............. .............. ....... 212 figure 23.3. pca interrupt blo ck diagram ................. ................ ................. ........... 213 figure 23.4. pca captur e mode diagram............. .............. .............. .............. ....... 214 figure 23.5. pca software time r mode diagram ........ ................. ................ ......... 215 figure 23.6. pca high speed output mode diagram........... ............... ........... ....... 216 figure 23.7. pca fr equency output mode ......... .............. .............. .............. ......... 217 figure 23.8. pca 8-bit pwm mode diagram .......... .............. ............... ........... ....... 218 figure 23.9. pca 16-bit pwm mode ................ ................. .............. .............. ......... 219 figure 23.10. pca module 2 with watchdog ti mer enabled ..... ................. ........... 220 24. c2 interface figure 24.1. typical c2 pin sharing.......... ................. ................ ................. ........... 229
c8051f350/1/2/3 10 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 11 list of tables 1. system overview table 1.1. product select ion guide ................. ................. .............. .............. ........... 18 2. absolute maximum ratings table 2.1. absolute maximum rati ngs ................... .............. ............... ........... ......... 29 3. global dc electrical characteristics table 3.1. global dc electrical characteristics ........... ................. ................ ........... 30 4. pinout and package definitions table 4.1. pin definitions for the c8051f350/1/2/3 ..... ................. ................ ........... 31 table 4.2. lqfp-32 package dime nsions ................ ................ ................. ............. 36 table 4.3. qfn-28 package dimensions ........... .............. .............. .............. ........... 37 5. 24 or 16-bit analog to digital converter (adc0) table 5.1. adc0 unipol ar output word coding (ad0pol = 0) .............. ................ 47 table 5.2. adc0 bipolar output word coding (ad0pol = 1) ................ ................ 47 table 5.3. adc0 elec trical characteristics .... ................ ................. .............. ........... 61 table 5.4. adc0 si nc3 filter typical rms no ise (v) ................. .............. ........... 62 table 5.5. adc0 sinc3 filter effective resolution in unipolar mode (bits) ... ................. .............. .............. .............. ........... 63 table 5.6. adc0 sinc3 filter flicker-free (noise-free) resolution in unipolar mode (bits) ... ................. .............. .............. .............. ........... 63 table 5.7. adc0 fast f ilter typical rms noise (v) .......... ............... ........... ......... 64 table 5.8. adc0 fast filter effective resolution in un ipolar mode (bits) ............... 64 table 5.9. adc0 fast filter flicker-free (n oise-free) resolution in unipolar mode (bits) ... ................. .............. .............. .............. ........... 65 6. 8-bit current mode dacs (ida0 and ida1) table 6.1. idac electrical char acteristics .............. .............. ............... ........... ......... 72 7. voltage reference table 7.1. voltage reference elec trical characteristi cs .............. ................ ........... 75 8. temperature sensor table 8.1. temperature sensor electrical characteri stics ........ ................. ............. 77 9. comparator0 table 9.1. comparator electrical characteristics ... .............. ............... ........... ......... 85 10. cip-51 microcontroller table 10.1. cip-51 instruction set summary ............ ................ ................. ............. 89 11. memory organization and sfrs table 11.1. special func tion register (sfr) memory map . ............... ........... ....... 101 table 11.2. special functi on registers .............. .............. .............. .............. ......... 102 12. interrupt handler table 12.1. interrupt summ ary ................. ................. ................ ................. ........... 106 13. prefetch engine 14. reset sources table 14.1. reset electrical char acteristics ........... .............. ............... ........... ....... 120 15. flash memory table 15.1. flash electric al characteristics ....... .............. .............. .............. ......... 126
c8051f350/1/2/3 12 rev. 1.0 16. external ram 17. oscillators table 17.1. oscillator el ectrical characteristics ............ ................. .............. ......... 136 18. port input/output table 18.1. port i/o dc electrical characteristics ............ .............. .............. ......... 150 19. smbus table 19.1. smbus clock source selection .............. ................ ................. ........... 156 table 19.2. minimum sda setup and hold times ...... ................. ................ ......... 157 table 19.3. sources for hardwa re changes to smb0cn ......... ................. ........... 161 table 19.4. smbus status decoding ............... ................. .............. .............. ......... 167 20. uart0 table 20.1. timer settings for standard baud rates using the internal osci llator ............ .............. .............. .............. ......... 178 table 20.2. timer settings for standard baud rates using an external 25.0 mhz oscillator .......... .............. .............. ......... 178 table 20.3. timer settings for standard baud rates using an external 22.1184 mh z oscillator .... .............. .............. ......... 179 table 20.4. timer settings for standard baud rates using an external 18.432 mhz oscillator ...... .............. .............. ......... 179 table 20.5. timer settings for standard baud rates using an external 11.0592 mh z oscillator .... .............. .............. ......... 180 table 20.6. timer settings for standard baud rates using an external 3.6864 mhz oscillator ...... .............. .............. ......... 180 21. serial periphera l interface (spi0) table 21.1. spi slave timing para meters ......... .............. .............. .............. ......... 193 22. timers 23. programmable counter array table 23.1. pca timebase input op tions ............ .............. .............. .............. ....... 212 table 23.2. pca0cpm register settings for pca captur e/compare modules .... 213 table 23.3. watchdog timer timeout intervals1 ......... ................. ................ ......... 221 24. c2 interface
c8051f350/1/2/3 rev. 1.0 13 list of registers sfr definition 5.1. adc0cn: adc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 sfr definition 5.2. adc0cf: adc0 c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 sfr definition 5.3. adc0md: adc0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 sfr definition 5.4. adc0cl k: adc0 modulator clock divisor . . . . . . . . . . . . . . . . . . 51 sfr definition 5.5. adc0dech: adc0 decimati on ratio register high byte . . . . . . 51 sfr definition 5.6. adc0decl: adc0 decimation ratio register low byte . . . . . . . 52 sfr definition 5.7. adc0dac: adc0 offset dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 sfr definition 5.8. adc0bu f: adc0 input buffer c ontrol . . . . . . . . . . . . . . . . . . . . . 53 sfr definition 5.9. adc0sta: adc0 st atus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 sfr definition 5.10. adc0coh: adc0 offset calibration regist er high byte . . . . . . 55 sfr definition 5.11. adc0com: ad c0 offset calibration regist er middle byte . . . . 55 sfr definition 5.12. adc0col: a dc0 offset calibration regist er low byte . . . . . . . 55 sfr definition 5.13. adc0cgh: adc0 gain cali bration register high by te . . . . . . . 56 sfr definition 5.14. adc0cgm: adc0 gain calib ration register middle byte . . . . . 56 sfr definition 5.15. adc0cgl: a dc0 gain calibration register low byte . . . . . . . . 56 sfr definition 5.16. adc0h: ad c0 conversion register (sinc3 filter) high byte . . 57 sfr definition 5.17. adc0m: adc0 conversion register (s inc3 filter) middle byte 57 sfr definition 5.18. adc0l: a dc0 conversion register (sinc3 filter) low byte . . . 57 sfr definition 5.19. ad c0fh: adc0 conversion register (fast filter) high byte . . . 58 sfr definition 5.20. adc0fm: ad c0 conversion register (fas t filter) middle byte . 58 sfr definition 5.21. adc0fl: ad c0 conversion register (fast filter) low byte . . . . 58 sfr definition 5.22. adc0mux: a dc0 analog multiplexer control . . . . . . . . . . . . . . 60 sfr definition 6.1. ida0cn: ida0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 sfr definition 6.2. ida0: ida0 data word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 sfr definition 6.3. ida1cn: id a1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 sfr definition 6.4. ida1: ida1 data word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 sfr definition 7.1. ref0cn: reference control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 sfr definition 9.1. cpt0cn : comparator0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 sfr definition 9.2. cpt0md : comparator0 mode selection . . . . . . . . . . . . . . . . . . . . 82 sfr definition 9.3. cpt0mx : comparator0 mux select ion . . . . . . . . . . . . . . . . . . . . 84 sfr definition 10.1. sp: stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 sfr definition 10.2. dpl: data pointe r low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 sfr definition 10.3. dph: da ta pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 sfr definition 10.4. psw: program st atus word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 sfr definition 10.5. acc: ac cumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 10.6. b: b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 10.7. pc on: power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 sfr definition 12.1. ie: inte rrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 sfr definition 12.2. ip: interr upt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 sfr definition 12.3. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . . 109 sfr definition 12.4. eip1: extended interrupt priority 1 . . . . . . . . . . . . . . . . . . . . . . 110 sfr definition 12.5. it01cf: int0/i nt1 configuration . . . . . . . . . . . . . . . . . . . . . . . 112 sfr definition 13.1. pfe0cn: prefet ch engine control . . . . . . . . . . . . . . . . . . . . . . 113
c8051f350/1/2/3 14 rev. 1.0 sfr definition 14.1. vdm0cn : vdd monitor control . . . . . . . . . . . . . . . . . . . . . . . . 117 sfr definition 14.2. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 sfr definition 15.1. psctl: program store r/w control . . . . . . . . . . . . . . . . . . . . . 125 sfr definition 15.2. flkey: flash lock and key . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 sfr definition 15.3. flscl: flash scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 sfr definition 16.1. emi0 cn: external memory interface cont rol . . . . . . . . . . . . . . 127 sfr definition 17.1. oscicn: inter nal oscillator control . . . . . . . . . . . . . . . . . . . . . 130 sfr definition 17.2. oscicl: intern al oscillator calibration . . . . . . . . . . . . . . . . . . . 130 sfr definition 17.3. oscxcn: external oscillator c ontrol . . . . . . . . . . . . . . . . . . . . 134 sfr definition 17.4. clkmul : clock multiplier control . . . . . . . . . . . . . . . . . . . . . . . 135 sfr definition 17.5. clksel: clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 sfr definition 18.1. xbr0: port i/o crossbar regist er 0 . . . . . . . . . . . . . . . . . . . . . 142 sfr definition 18.2. xbr1: port i/o crossbar regist er 1 . . . . . . . . . . . . . . . . . . . . . 143 sfr definition 18.3. p0: port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 sfr definition 18.4. p0mdin : port0 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 sfr definition 18.5. p0mdout: port 0 output mode . . . . . . . . . . . . . . . . . . . . . . . . . 146 sfr definition 18.6. p0ski p: port0 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 sfr definition 18.7. p1: port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 sfr definition 18.8. p1mdin : port1 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 sfr definition 18.9. p1mdout: port 1 output mode . . . . . . . . . . . . . . . . . . . . . . . . . 148 sfr definition 18.10. p1 skip: port1 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 sfr definition 18.11. p2: port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 sfr definition 18.12. p2mdout: port 2 output mode . . . . . . . . . . . . . . . . . . . . . . . . 149 sfr definition 19.1. smb0cf: smbu s clock/configuration . . . . . . . . . . . . . . . . . . . 158 sfr definition 19.2. smb0cn : smbus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 sfr definition 19.3. smb0dat: smbus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 sfr definition 20.1. scon0: serial port 0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 176 sfr definition 20.2. sbuf0: serial (uart0) port data buffer . . . . . . . . . . . . . . . . . 177 sfr definition 21.1. spi0cf g: spi0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 187 sfr definition 21.2. spi0cn: spi0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 sfr definition 21.3. spi0ck r: spi0 clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 sfr definition 21.4. spi0dat: spi0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 sfr definition 22.1. tcon: timer contro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 sfr definition 22.2. tmod: ti mer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 sfr definition 22.3. ckcon: clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 sfr definition 22.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 sfr definition 22.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 sfr definition 22.6. th0: timer 0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 sfr definition 22.7. th1: timer 1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 sfr definition 22.8. tmr2cn: timer 2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 sfr definition 22.9. tmr2rll: ti mer 2 reload register low byte . . . . . . . . . . . . . 206 sfr definition 22.10. tmr2 rlh: timer 2 reload re gister high byte . . . . . . . . . . . 206 sfr definition 22.11. tmr2l: timer 2 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 sfr definition 22.12. tmr2h timer 2 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 sfr definition 22.13. tmr3cn: timer 3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
c8051f350/1/2/3 rev. 1.0 15 sfr definition 22.14. tmr3 rll: timer 3 reload regi ster low byte . . . . . . . . . . . . 210 sfr definition 22.15. tmr3 rlh: timer 3 reload re gister high byte . . . . . . . . . . . 210 sfr definition 22.16. tmr3l: timer 3 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 sfr definition 22.17. tmr3h timer 3 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 sfr definition 23.1. pca0cn: pca control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 sfr definition 23.2. pca0md: pca mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 sfr definition 23.3. pc a0cpmn: pca capture/compare mode . . . . . . . . . . . . . . . 224 sfr definition 23.4. pca0l: pca counter/timer low byte . . . . . . . . . . . . . . . . . . . 225 sfr definition 23.5. pca0h: pca counter/timer high byte . . . . . . . . . . . . . . . . . . . 225 sfr definition 23.6. pca0cpln: pca capture module low byte . . . . . . . . . . . . . . . 226 sfr definition 23.7. pca0cphn: pca capture module high byte . . . . . . . . . . . . . . 226 c2 register definition 24.1. c2add: c2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 c2 register definition 24.2. device id: c2 device id . . . . . . . . . . . . . . . . . . . . . . . . 227 c2 register definition 24.3. revid: c2 revision id . . . . . . . . . . . . . . . . . . . . . . . . . 228 c2 register definition 24.4. fp ctl: c2 flash programming cont rol . . . . . . . . . . . . 228 c2 register definition 24.5. fp dat: c2 flash programming data . . . . . . . . . . . . . . 228
c8051f350/1/2/3 16 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 17 1. system overview c8051f350/1/2/3 devices are fully integrated mixed-si gnal system-on-a-chip m cus. highlighted features are listed below. refer to ta b l e 1.1 for specific product feature selection. ? high-speed pipelined 8051-compatible microcontroller core (up to 50 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? 24 or 16-bit single-ended/differe ntial adc with analog multiplexer ? two 8-bit current output dacs ? precision programmable 24.5 mhz internal oscillator ? 8 kb of on-chip flash memory ? 768 bytes of on-chip ram ? smbus/i2c, enhanced uart, and spi serial interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with three capture/compare modules and watchdog timer function ? on-chip power-on reset, v dd monitor, and temperature sensor ? on-chip voltage comparator ? 17 port i/o (5 v tolerant) with on-chip power-on reset, v dd monitor, watchdog timer, and cl ock oscillator, th e c8051f350/1/2/3 devices are truly stand-alone system-on-a-chip solu tions. the flash memory can be reprogrammed even in-circuit, providing non-vo latile data storage, and also allowing field upgrades of the 8051 firmware. user software has complete control of all peripherals, and ma y individually shut down any or all peripherals for power savings. the on-chip silicon labs 2- wire (c2) development interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions , allowing in-system debugging with - out occupying package pins. each device is specified for 2.7 to 3.6 v operation over the industrial temperature range (?45 to +85 c). the port i/o and /rst pins are tolerant of input signals up to 5 v. the c8051f350/1/2/3 are available in 28-pin qfn (also referred to as mlp or mlf) or 32-pin lqfp packaging, as shown in figure 1.1 through figure 1.4 .
table 1.1. product selection guide ordering part number mips (peak) flash memory ram calibrated internal 24.5 mhz oscillator clock multiplier smbus/i2c spi uart timers (16-bit) programmable counter array digital port i/os 24-bit adc 16-bit adc two 8-bit current output dacs internal voltage reference temperature sensor analog comparator lead-free (rohs compliant) package c8051f350-gq 50 8 kb 768 3 3 3 3 3 4 3 17 3 ? 3 3 3 3 3 lqfp-32 C8051F351-gm 50 8 kb 768 3 3 3 3 3 4 3 17 3 ? 3 3 3 3 3 qfn-28 c8051f352-gq 50 8 kb 768 3 3 3 3 3 4 3 17 ? 3 3 3 3 3 3 lqfp-32 c8051f353-gm 50 8 kb 768 3 3 3 3 3 4 3 17 ? 3 3 3 3 3 3 qfn-28 c8051f350/1/2/3 18 rev. 1.0
port 0 latch uart 8 kb flash 256 byte sram por sfr bus 8 0 5 1 c o r e timer 0, 1, 2, 3 3-chnl pca/ wdt p 0 d r v x b a r reset system clock digital power debug hw smbus c2d c2d cp0 + - cp0+ p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 vdd gnd /rst/c2ck brown- out 24-bit adc0 a m u x ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 vref+ 512 byte xram spi bus p 1 d r v p1.0 p1.1 p1.2 p1.3 p1.4/cp0a p1.5/cp0 p1.6/idac0 p1.7/idac1 cp0- 8-bit idac0 8-bit idac1 port 1 latch vref pga analog power av+ agnd vref? temp sensor buffer + + offset dac p2.0/c2d port 2 latch cp0a xtal1 xtal2 external oscillator circuit 24.5 mhz 2% internal oscillator clock multiplier port 0 latch uart 8 kb flash 256 byte sram por sfr bus 8 0 5 1 c o r e timer 0, 1, 2, 3 3-chnl pca/ wdt p 0 d r v x b a r reset system clock digital power debug hw smbus c2d c2d cp0 + - cp0+ p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 vdd gnd /rst/c2ck brown- out 24-bit adc0 a m u x ain0 ain1 ain2 ain3 vref+ 512 byte xram spi bus p 1 d r v p1.0/ain4 p1.1/ain5 p1.2/ain6 p1.3/ain7 p1.4/cp0a p1.5/cp0 p1.6/idac0 p1.7/idac1 cp0- 8-bit idac0 8-bit idac1 port 1 latch vref pga analog power av+ agnd vref? temp sensor buffer + + offset dac p2.0/c2d port 2 latch cp0a ain4-7 ain4 ain5 ain6 ain7 xtal1 xtal2 external oscillator circuit 24.5 mhz 2% internal oscillator clock multiplier c8051f350/1/2/3 rev. 1.0 19 figure 1.1. c8051f350 block diagram figure 1.2. C8051F351 block diagram
port 0 latch uart 8 kb flash 256 byte sram por sfr bus 8 0 5 1 c o r e timer 0, 1, 2, 3 3-chnl pca/ wdt p 0 d r v x b a r reset system clock digital power debug hw smbus c2d c2d cp0 + - cp0+ p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 vdd gnd /rst/c2ck brown- out 16-bit adc0 a m u x ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 vref+ 512 byte xram spi bus p 1 d r v p1.0 p1.1 p1.2 p1.3 p1.4/cp0a p1.5/cp0 p1.6/idac0 p1.7/idac1 cp0- 8-bit idac0 8-bit idac1 port 1 latch vref pga analog power av+ agnd vref? temp sensor buffer + + offset dac p2.0/c2d port 2 latch cp0a xtal1 xtal2 external oscillator circuit 24.5 mhz 2% internal oscillator clock multiplier port 0 latch uart 8 kb flash 256 byte sram por sfr bus 8 0 5 1 c o r e timer 0, 1, 2, 3 3-chnl pca/ wdt p 0 d r v x b a r reset xtal1 xtal2 external oscillator circuit system clock 24.5 mhz 2% internal oscillator digital power debug hw smbus c2d c2d cp0 + - cp0+ p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 vdd gnd /rst/c2ck brown- out 16-bit adc0 a m u x ain0 ain1 ain2 ain3 vref+ 512 byte xram spi bus p 1 d r v p1.0/ain4 p1.1/ain5 p1.2/ain6 p1.3/ain7 p1.4/cp0a p1.5/cp0 p1.6/idac0 p1.7/idac1 cp0- 8-bit idac0 8-bit idac1 port 1 latch vref pga analog power av+ agnd vref? temp sensor buffer + + offset dac x2 p2.0/c2d port 2 latch cp0a ain4-7 ain4 ain5 ain6 ain7 c8051f350/1/2/3 20 rev. 1.0 figure 1.3. c8051f352 block diagram figure 1.4. c8051f353 block diagram
c8051f350/1/2/3 rev. 1.0 21 1.1. cip-51? microcontroller 1.1.1. fully 8051 compatible instruction set the c8051f35x devices use silicon l abs? proprietary cip-51 microcontr oller core. the cip-51 is fully compatible with the mcs-51? instruction set. standard 803x/805x assemblers and compilers can be used to develop software. the c8051f35x family has a superset of all the peripherals included with a standard 8052. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 to 24 mhz. by contrast, the cip- 51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's syst em clock running at 50 mhz, it has a peak throughput of 50 mips. the cip-51 has a total of 109 instructions. the table below shows the tota l number of instructions th at require each execution time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 1.1.3. additional features the c8051f350/1/2/3 soc family includes several key enhancements to the cip-51 core and peripherals to improve performance and ease of use in end applications. an extended interrupt handler allows the numerous analog and digital peripherals to operate indepen - dently of the controller core and interrupt the controlle r only when necessary. by requiring less intervention from the microcontroller core, an interrupt-driven syste m is more efficient and allows for easier implemen - tation of multi-tasking, real-time systems. eight reset sources are available: power-on reset circuitry (por), an on-chip v dd monitor, a watchdog timer, a missing clock detector, a voltage level detect ion from comparator0, a forced software reset, an external reset pin, and an illegal fl ash access protection circuit. each reset sour ce except for the por, reset input pin, or flash error may be disabled by the user in software. the wdt may be permanently enabled in software after a power -on reset during mcu initialization. the internal oscillator is factory calibrated to 24.5 mhz 2%. an external oscillato r drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, rc, or cmos clock source to generate the system clock. a clock multiplier allows for operation at up to 50 mhz. an external oscillator can also be extremely useful in low power applications, allowing th e mcu to run from a slow (power saving) source, while periodically switching to the fast internal oscillator as needed.
c8051f350/1/2/3 22 rev. 1.0 1.2. on-chip debug circuitry the c8051f350/1/2/ 3 devices include on-chip silicon labs 2-wire (c2) debug circuitry that provides non- intrusive, full speed, in-circuit debugging of the production part installed in the end application. silicon labs' debugging syst em supports inspection and modificati on of memory and registers, break - points, and single stepping. no additional target ram, program memory, timers, or communications chan - nels are required. all the digital and analog periphera ls are functional and work correctly while debugging. all the peripherals (except for the adc and smbus) are stalled when the mcu is halted, during single stepping, or at a breakpoint in order to keep them synchronized. the c8051f350dk development kit provides all the har dware and software necessary to develop applica - tion code and perform in-circuit debugging with the c8051f35x mcus. the kit includes software with a developer's studio and debugger, a c2 debug adapter, a target application board with the associated mcu installed, and the required cables and wall-mount power supply. the development kit requires a computer with windows 98 se or later installed. the silicon labs ide interface is a vastly superior developing and debu gging configuratio n, compared to standard mcu emulators that use on-board "ice chips" and require the mcu in the application board to be socketed. silicon labs' debug para digm increases ease of use and preserves the performance of the precision analog peripherals. target pcb debug adapter vdd gnd c2 (x2), vdd, gnd windows 98 se or later silicon labs integrated development environment c8051f350 figure 1.5. development/in -system debug diagram
c8051f350/1/2/3 rev. 1.0 23 1.3. on-chip memory the cip-51 has a standard 8051 program and data addr ess configuration. it in cludes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128 byte sfr addre ss space. the lower 128 bytes of ram are accessible via direct and indirect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 byte s can be byte addressable or bit addressable. program memory consists of 8 kb bytes of flash. this memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 512 bytes (accessable using movx instruction) 0x0000 0x01ff same 512 bytes as from 0x0000 to 0x01ff, wrapped on 512-byte boundaries 0x0200 0xffff 8k flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x1e00 0x1dff 0x1fff figure 1.6. memory map
c8051f350/1/2/3 24 rev. 1.0 1.4. 24 or 16-bit analog to digital converter (adc0) the c8051f350/1/2/3 include a fully-differential, 24 -bit (c8051f350/1) or 16-bit (c8051f352/3) sigma- delta analog to digital converter (adc) with on-chip calibration capabiliites. tw o separate decimation fil - ters can be programmed for throughputs of up to 1 khz. an internal 2.5 v reference is available, or a differ - ential external reference can be used for ratiom etric measurements. a programmable gain amplifier (pga) is included, with eight gain settings up to 1 28x. an analog front-end multiplexer connects the differ - ential inputs to eight external pins, the internal te mperature sensor, or agnd. the on-chip input buffers can be used to provide a high input impedance for direct connection to sensitive transducers. an 8-bit off - set dac allows for correction of large input offset voltages. ain+ ain- av+ agnd input buffers 8-bit offset dac
c8051f350/1/2/3 rev. 1.0 25 1.5. two 8-bit current-mode dacs the c8051f350/1/2/3 devices include two 8-bit curr ent-mode digital-to-analog converters (idacs). the maximum current output of the idacs can be adjusted for four different current settings; 0.25 ma, 0.5 ma, 1 ma, and 2 ma. a flexible output update mechanism allows for seamless full-scale changes, and supports jitter-free update s for waveform generation. idac updates ca n be performed on-demand, scheduled on a timer overflow, or synchronized with an external signal. figure 1.8 shows a block diagram of the idac cir - cuitry. ida0 8 latch 8 current output 8-bit digital input ida1 8 latch 8 current output 8-bit digital input data write timer 0 timer 1 timer 2 timer 3 cnvstr data write timer 0 timer 1 timer 2 timer 3 cnvstr figure 1.8. idac block diagram
c8051f350/1/2/3 26 rev. 1.0 1.6. programmable comparator c8051f350/1/2/3 devices include a software-configurable voltage comparator with an input multiplexer. the comparator offers programmable response time and hysteresis and two ou tputs that are optionally available at the port pins: a synchronous ?latched? ou tput (cp0), or an asynchronous ?raw? output (cp0a). comparator interrupts may be generated on rising, fallin g, or both edges. when in idle mode, these inter - rupts may be used as a ?wake-up? source for the proc essor. comparator0 may also be configured as a reset source. a block diagram of the comparator is shown in figure 1.9 . vdd reset decision tree + - q q set clr d q q set clr d (synchronizer) gnd cp0 (synchronous output) cp0a (asynchronous output) interrupt logic multiplexer port i/o pins figure 1.9. comparator0 block diagram 1.7. serial ports the c8051f350/1/2/3 family includes an smbus/i2c interface, a full-duplex uart with enhanced baud rate configuration, and an enhanced spi interface. ea ch of the serial buses is fully implemented in hard - ware and makes extensive use of t he cip-51's interrupts, thus requiring very little cpu intervention.
c8051f350/1/2/3 rev. 1.0 27 1.8. port input/output c8051f350/1/2/3 devices include 17 i/o pins. port pins are organized as two byte-wide ports and one 1-bit port. the port pins behave like typical 8051 ports with a few enhancements. each port pin can be config - ured as a digital or analog i/o pin. pins selected as di gital i/o can be configured for push-pull or open-drain operation. the ?weak pull-ups? that are fixed on ty pical 8051 devices may be globally disabled to save power. the digital crossbar allows mappin g of internal digital system resources to port i/o pins. on-chip conter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the port pins using the crossbar control resgiters. this allows the user to select the exact mix of general- purpose port i/o, digital, and analog resources needed for the application. xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 pnmdout, pnmdin registers uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 4 pca 4 spi cp0 outputs 2 p1 i/o cells p1.0 p1.7 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 p2 (p2.0) p2 i/o cell p2.0 figure 1.10. port i/o fun ctional block diagram
c8051f350/1/2/3 28 rev. 1.0 1.9. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. the counte r/timer is driven by a programmable timebase that can select between six sources: syst em clock, system clock divided by four, system clock divided by twelve, the external oscillator clock so urce divided by 8, timer 0 overflow, or an external clock signal on the external clock nput (eci) input pin. each capture/compare module may be configured to operate independently in one of six modes: edge- triggered capture, software timer, high-speed out put, frequency output, 8-bit pwm, or 16-bit pwm. additionally, pca module 2 may be used as a watchdog timer (wdt), and is enabled in this mode follow - ing a system reset. the pca capture/compare module i/o and the external clock input may be routed to port i/o using the digital crossbar. capture/compare module 1 capture/compare module 0 capture/compare module 2 / wdt cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 figure 1.11. pca block diagram
c8051f350/1/2/3 rev. 1.0 29 2. absolute maximum ratings table 2.1. absolute maximum ratings ?55 125 c ?65 150 c ?0.3 v dd + 0.3 v ?0.3 5.8 v ?0.3 4.2 v ?0.3 4.2 v 100 ma 50 ma 100 ma 50 ma 500 ma note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specif ication is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. parameter conditions min typ max units ambient temperature under bias storage temperature voltage on any pin (except v dd , av+, and port i/o) with respect to dgnd voltage on any port i/o pin or /rst with respect to dgnd voltage on v dd with respect to dgnd voltage on av+ with respect to agnd maximum output current sunk by any port pin maximum output current sunk by any other i/o pin maximum output current sourced by any port pin maximum output current sourced by any other i/o pin maximum total current through v dd , av+, dgnd, and agnd
c8051f350/1/2/3 30 rev. 1.0 3. global dc electrical characteristics table 3.1. global dc electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. 2.7 3.0 3.6 v 800 a < 1 a 0.5 v 2.7 3.0 3.6 v 10 14 ma ma 5.5 7.0 ma ma < 0.1 a 1.5 v 0 50 mhz ?40 +85 c notes: 1. analog supply av+ must be greater than 1 v for v dd monitor to operate. 2. sysclk is the internal device clo ck. for operational speeds in excess of 25 mhz, sysclk must be derived from the internal clock multiplier. 3. sysclk must be at least 32 khz to enable debugging. parameter conditions min typ max units analog supply voltage 1 analog supply current internal ref, adc, idacs, comparators all active analog supply current with ana- log sub-systems inactive internal ref, adc, idacs, comparators all disabled, oscillator disabled analog-to-digital supply delta (|v dd ? av+|) digital supply voltage digital supply current with cpu active v dd = 2.7 v v dd = 3.3 v digital supply current with cpu inactive (not accessing flash) v dd = 2.7 v v dd = 3.3 v digital supply current (shut- down) oscillator not running digital supply ram data reten- tion voltage sysclk (system clock) 2,3 specified operating tempera- ture range
c8051f350/1/2/3 rev. 1.0 31 4. pinout and package definitions table 4.1. pin definitions for the c8051f350/1/2/3 name pin numbers type description ?f350 ?f352 ?f351 ?f353 v dd 21 17 power digital supply voltage. must be tied to +2.7 v to +3.6 v power. dgnd 22 18 ground digital ground. must be tied to ground. av+ 10 6 power analog supply voltage. must be tied to +2.7 v to +3.6 v power. agnd 9 5 ground analog ground. must be tied to ground. /rst c2ck 12 8 d i/o d i/o device reset. open-drain output of internal por or v dd monitor. an external source can initiate a system reset by driving this pin low for at least 15 s. a 1k ? pull-up to v dd is recommended. see reset sources section. clock signal for the c2 debug interface. p2.0/ c2d 11 7 d i/o d i/o port 2.0. see port i/o section for a complete description. bi-directional data signal for the c2 debug interface. p0.0 13 9 d i/o or a in port 0.0. see port i/o section for a complete description. p0.1 14 10 d i/o or a in port 0.1. see port i/o section for a complete description. p0.2/ xtal1 15 11 d i/o or a in a in port 0.2. see port i/o section for a complete description. this pin is the external oscilla tor return for a crystal or reso - nator. see oscillator section. p0.3/ xtal2 16 12 d i/o a i/o or d in port 0.3. see port i/o section for a complete description. this pin is the excitation driver for an external crystal or res - onator, or an external clock input for cmos, capacitor, or rc oscillator configurations . see oscillator section. p0.4 17 13 d i/o or a in port 0.4. see port i/o section for a complete description. p0.5 18 14 d i/o or a in port 0.5. see port i/o section for a complete description.
c8051f350/1/2/3 32 rev. 1.0 p0.6/ cnvstr 19 15 d i/o or a in d in port 0.6. see port i/o section for a complete description. external convert start input for idacs (see idac section for complete description). p0.7 20 16 d i/o or a in port 0.7. see port i/o section for a complete description. p1.0/ ain0.4 23 19 d i/o or a in a in port 1.0. see port i/o section for a complete description. adc0 input channel 4 (C8051F351/3 - see adc0 section for complete description). p1.1/ ain0.5 24 20 d i/o or a in a in port 1.1. see port i/o section for a complete description. adc0 input channel 5 (C8051F351/3 - see adc0 section for complete description). p1.2/ ain0.6 25 21 d i/o or a in a in port 1.2. see port i/o section for a complete description. adc0 input channel 6 (C8051F351/3 - see adc0 section for complete description). p1.3/ ain0.7 26 22 d i/o or a in a in port 1.3. see port i/o section for a complete description. adc0 input channel 7 (C8051F351/3 - see adc0 section for complete description). p1.4 27 23 d i/o or a in port 1.4. see port i/o section for a complete description. p1.5 28 24 d i/o or a in port 1.5. see port i/o section for a complete description. p1.6/ ida0 29 25 d i/o or a in a out port 1.6. see port i/o section for a complete description. idac0 output (see idac sect ion for complete description). p1.7/ ida1 30 26 d i/o or a in a out port 1.7. see port i/o section for a complete description. idac1 output (see idac sect ion for complete description). table 4.1. pin definitions for the c8051f350/1/2/3 (continued) name pin numbers type description ?f350 ?f352 ?f351 ?f353
c8051f350/1/2/3 rev. 1.0 33 ain0.0 1 1 a in adc0 input channel 0 (see adc0 section for complete description). ain0.1 2 2 a in adc0 input channel 1 (see adc0 section for complete description). ain0.2 3 3 a in adc0 input channel 2(see adc0 section for complete description). ain0.3 4 4 a in adc0 input channel 3 (see adc0 section for complete description). ain0.4 5 ? a in adc0 input channel 4 (c8051f350/2 - see adc0 section for complete description). ain0.5 6 ? a in adc0 input channel 5 (c8051f350/2 - see adc0 section for complete description). ain0.6 7 ? a in adc0 input channel 6 (c8051f350/2 - see adc0 section for complete description). ain0.7 8 ? a in adc0 input channel 7 (c8051f350/2 - see adc0 section for complete description). vref+ 31 27 a i/o vref positive voltage pin (see vref section for complete description). vref? 32 28 a i/o vref negative voltage pin (see vref section for com - plete description). table 4.1. pin definitions for the c8051f350/1/2/3 (continued) name pin numbers type description ?f350 ?f352 ?f351 ?f353
1 ain0.7 p1.1 p0.6 dgnd p1.0 vdd ain0.3 ain0.4 ain0.2 ain0.0 ain0.1 p0.5 p0.4 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p0.7 c8051f350 c8051f352 top view ain0.5 ain0.6 agnd av+ p2.0 / c2d /rst / c2ck p0.0 p0.1 p1.2 p1.3 p1.4 p1.5 p1.7 / ida1 vref+ vref- p1.6 / ida0 p0.2 / xtal1 p0.3 / xtal2 c8051f350/1/2/3 34 rev. 1.0 figure 4.1. lqfp-32 pi nout diagram (top view)
4 5 6 7 2 1 3 11 12 13 14 9 8 10 18 17 16 15 20 21 19 25 26 27 28 23 22 24 C8051F351 c8051f353 top view ain0.0 ain0.1 ain0.2 ain0.3 agnd av+ p2.0 / c2d /rst / c2ck p0.0 p0.1 p0.2 / xtal1 p0.3 / xtal2 p0.4 p0.5 p0.6 p0.7 vdd dgnd p1.0 / ain0.4 p1.1 / ain0.5 p1.2 / ain0.6 p1.3 / ain0.7 p1.4 p1.5 p1.6 / ida0 p1.7 / ida1 vref+ vref- gnd gnd c8051f350/1/2/3 rev. 1.0 35 figure 4.2. qfn-28 pino ut diagram (top view)
table 4.2. lqfp-32 package dimensions mm min typ max a??1.60 a1 0.05 ? 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 d ? 9.00 ? d1 ? 7.00 ? e ? 0.80 ? e ? 9.00 ? e1 ? 7.00 ? l 0.45 0.60 0.75 pin 1 identifier a1 e b 1 32 e1 d1 d e a2 a l c8051f350/1/2/3 36 rev. 1.0 figure 4.3. lqfp-32 package diagram
c8051f350/1/2/3 rev. 1.0 37 1 e d a2 a a1 e a3 e2 r e l bottom view side view 2 3 4 5 6 7 8 9 10 12 13 14 21 20 19 17 16 15 28 27 26 24 23 22 e2 25 2 d2 11 18 d2 2 6 x e 6 x e detail 1 detail 1 aa bb cc dd b table 4.3. qfn-28 package dimensions mm min typ max a 0.80 0.90 1.00 a1 0 0.02 0.05 a2 0 0.65 1.00 a3 ? 0.25 ? b 0.18 0.23 0.30 d?5.00? d2 2.90 3.15 3.35 e?5.00? e2 2.90 3.15 3.35 e?0.5? l 0.45 0.55 0.65 n?28? nd ? 7 ? ne ? 7 ? r0.09? ? aa ? 0.435 ? bb ? 0.435 ? cc ? 0.18 ? dd ? 0.18 ? figure 4.4. qfn-28 package drawing
c8051f350/1/2/3 38 rev. 1.0 b l 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm e e d 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm top view e2 d2 0.20 mm 0.20 mm 0.50 mm 0.50 mm figure 4.5. typical qf n-28 landing diagram
b l 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm e e d 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm top view e2 d2 0.20 mm 0.20 mm 0.50 mm 0.50 mm 0.30 mm 0.20 mm 0.60 mm 0.40 mm 0.70 mm 0.60 mm c8051f350/1/2/3 rev. 1.0 39 figure 4.6. typical qfn- 28 solder paste diagram
c8051f350/1/2/3 40 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 41 5. 24 or 16-bit analog to digital converter (adc0) the c8051f350/1/2/3 include a fully-differential, 24 -bit (c8051f350/1) or 16-bit (c8051f352/3) sigma- delta analog to digital converter (adc) with on-chip calibration capabiliites. tw o separate decimation fil - ters can be programmed for throughputs of up to 1 khz. an internal reference is available, or a differential external reference can be used for ratiometric measurements. a programmable gain amplifier (pga) is included, with eight gain settings up to 128x. the on-c hip input buffers can be used to provide a high input impedance for direct connection to sensitive transducers. an 8-bit offset dac allows for correction of large input offset voltages. ain+ ain- av+ agnd ad0bce ad0bce input buffers adc0buf 8-bit offset dac adc0dac
c8051f350/1/2/3 42 rev. 1.0 5.1. configuration adc0 is enabled by setting the ad0en bit in register adc0md (sfr definition 5.3) to ?1?. when the adc is disabled, it is placed in a low-power shutdown mode with all clocks turned off, to minimize unnecessary power consumption. the a dc will retain all of its settings in shut down mode, with the exception of the ad0sm bits, which are reset to 000b (idle mode). 5.1.1. voltage reference selection the adc?s voltage reference is selected using the ad 0vref bit in register adc0cf (sfr definition 5.2). when set to ?1?, the adc uses an external voltage reference source. when cleared to ?0?, the internal refer - ence is used. a more detailed description of the voltage reference options can be found in section ?7. voltage reference? on page 73 . 5.1.2. analog inputs the adc?s analog inputs are connected to external de vice pins or internal voltages as described in sec - tion ?5.6. analog multiplexer? on page 59 . they can be configured as either single-ended (one indepen - dent input measured with respect to agnd) or differ ential (two independent in puts measured with respect to each other). for accurate measurements, the adc inputs must remain within the input range specifica - tions found in table 5.3 . to prevent damage to the device, all exte rnal adc inputs must also remain within the absolute maximum ratings for the input pin, given in ta b l e 2.1 . 5.1.2.1. programmable gain amplifier a programmable gain amplifier (pga) pr ovides amplification settings of 1, 2, 4, 8, 16, 32, 64, and 128 for the adc inputs. the pga gain setting is contro lled by the ad0gn bits in register adc0cn ( sfr definition 5.1 ). 5.1.2.2. input buffers independent input buffers are included for ain+ and ain?, as shown in figure 5.2. each input has a set of two buffers that can be used to minimize the input current of the adc for sensitive measurements. the ?low? input buffer can be used when the absolute pin input voltage is in the lower half of the supply range. the ?high? input buffer on each pin can be used when the absolute pin input voltage is in the upper half of the supply range. see table 5.3 for the input buffer range specifications. the input buffers can also be bypassed, for a direct connection to the pga inputs. the adc input buffers are controlled with the adc0buf register ( sfr definition 5.8 ).
low buffer+ high buffer+ bypass buffer low buffer- high buffer- bypass buffer adc0buf ad0bphe ad0bple ad0bps1 ad0bps0 ad0bnhe ad0bnle ad0bns1 ad0bns0 ain+ channel to pga to pga ain- channel c8051f350/1/2/3 rev. 1.0 43 figure 5.2. adc0 buffer control 5.1.3. modulator clock the adc0clk register (sfr definition 5.4) holds the modulator clock (mdclk) divisor value. the modu - lator clock determines the switchin g frequency for the adc sampling ca pacitors. optimal performance will be achieved when the mdclk frequency is equal to 2.4576 mhz. the modulator samples the input at a rate of mdclk / 128. 5.1.4. decimation ratio the decimation ratio of the adc filters is selected by the dec i[10:0] bits in the adc0dech and adc0decl registers ( sfr definition 5.5 and sfr definition 5.6 , respectively). the decimation ratio is equal to 1 + deci[10:0]. the decimation ratio determines how many modulator samples are used to gen - erate a single output word. the adc output word rate is equal to the modulator sampling rate divided by the decimation ratio. for more information on ho w the adc output word rate is derived, see sfr definition 5.4 and sfr definition 5.6 . higher decimation ratios will produce lower-noise results over a longer conver - sion period. the minimum decimation ratio is 20. when using the fast filter output, the decimation ratio must be set to a multiple of 8.
c8051f350/1/2/3 44 rev. 1.0 5.2. calibrating the adc adc0 can be calibrated in-system for both gain and offset, using internal or system calibration modes. to ensure calibration accu racy, offset calibrations must be performed prior to gain calibrations. it is not neces - sary to perform both inte rnal and system calibrations, as a system calibration will also compensate for any internal error sources. offset calibration is a single-point measurement that sets which input voltage produces a zero at the adc output. when performing an offset calibration, any devia tion from zero in the measurement is stored in the offset register. the offset value is subtract ed from all conversions as they take place. gain calibration is a two-point measurement that sets the slope of the adc transfer function. when per - formed, a gain calibration takes only a single measurement, which is assumed to be the desired full-scale value in the adc transfer function. the offset calibrati on value is used as the other point in the gain calibra - tion measurement, so that a gain factor can be calc ulated. after offset correction, conversions are multi - plied by the gain factor. calibrations are initiated by writing the adc system mode bits (ad0sm) to one of the calibration options. during a calibration, the ad0cbsy bit is set to ?1?. up on completion of a calibration the the ad0sm bits will return to idle mode, the ad0cbsy bi t will be cleared to ?0?, the ad0calc bit will be set to ?1?, and an adc interrupt will be generated. the ad0calc bit is cleared by clearing the ad0int flag. calibration results are also written to the appropriate calibration registers when the calibration is complete. 5.2.1. internal calibration internal calibration is performed without requiring a specific voltage on the adc input pins. internal calibra - tions can be performed in three different ways: offset only, gain only, or full (offset and gain). a full internal calibration consists of an internal of fset calibration followed by an internal gain calibration. if offset and gain calibrations are performed independently, offset calibration must be performed prior to gain calibration. during an internal offset calibration, the adc inputs ar e connected internally to agnd. for an internal gain calibration, the adc inputs are connected internally to a full-scale voltage that is equal to the selected volt - age reference divided by the pga gain. 5.2.2. system calibration system calibration is performed us ing voltages which are applied to the adc inputs. there are two system calibration options: offset calibration and gain calibration . for accurate calibration re sults, offset calibration must be performed prior to gain calibration. during a system offset calibration, the adc inputs should be connected to a ?zero? value. during a system gain cali bration, the adc inputs should be connected to the positive full-scale value for the current pga gain setting. 5.2.3. calibration coefficient storage the calibration results for offset and gain are each 24 -bits long. the calibration re sults are stored in sfrs that are both readable and writeable from software. this enables factory calibrations, as well as manual modification of the offset and gain parameters. the of fset calibration results are stored as a two?s comple - ment, 24-bit number in the adc0 coh, adc0com, and adc0col registers. the mapping of the offset register is shown in figure 5.3 . the gain calibration results are stored as a fixed-point, 24-bit number in the adc0cgh, adc0cgm, and adc0cgl registers. the mapping of the gain register is shown in figure 5.4 .
the offset calibration value adjusts the zero point of the adc?s transfer function. it is stored as a two?s complement, 24-bit number. an offset calibration which results in a full-scale positive (0x7fffff) or full- scale negative (0x800000 ) result will cause an adc error condition. the offset calibration results are stored in regist ers adc0coh, adc0com, an d adc0col. the weight- ing of the bits in the offset register (in lsbs) are shown below: 24-bit adc (c8051f350/1) adc0coh adc0com adc0col msb22212019181716151413121110987654321lsb ? 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 16-bit adc (c8051f352/3) adc0coh adc0com adc0col msb22212019181716151413121110987654321lsb ?2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 ?1 2 ?2 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 2 ?8 the gain calibration value adjusts the slope of the adc?s transfer function. the gain calibration regsiter can range from 0 to 2 ? 2 ?23 . a gain calibration which results in either of these ex tremes will cause an adc error condition. the gain calibration results are stored in regist ers adc0cgh, adc0cgm, an d adc0cgl, as follows: example decoding for gain register settin g of 0x940000 (10010100 00000000 00000000b): slope adjustment = 2 0 + 2 ?3 + 2 ?5 = 1.0 + 0.125 + 0.03125 = 1.15625 adc0cgh adc0cgm adc0cgl msb22212019181716151413121110 9 8 7 6 5 4 3 2 1lsb 2 0 2 ?1 2 ?2 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 2 ?8 2 ?9 2 ?10 2 ?11 2 ?12 2 ?13 2 ?14 2 ?15 2 ?16 2 ?17 2 ?18 2 ?19 2 ?20 2 ?21 2 ?22 2 ?23 c8051f350/1/2/3 rev. 1.0 45 figure 5.3. adc0 offset ca libration register coding figure 5.4. adc0 gain ca libration register coding
c8051f350/1/2/3 46 rev. 1.0 5.3. performing conversions the adc offers two conversion modes: single conver sion, and continuous conversion. in single conver - sion mode, a single conversion result is produced for each of the filters (sinc3 and fast). in continuous conversion mode, the adc will perf orm back-to-back co nversions until the adc mode is changed. proce - dures for single and continuous conversion modes are detailed in the sections below. 5.3.1. single conversions a single conversion is initiated by writing the adc system mode bits (ad0sm) to the ?single conversion? option. single conversion mode instru cts the adc to gather enough information to produce a result for the filter that is selected by the ad0isel bit. during the conversion, the ad0busy flag will be set to ?1?. the fast filter results will be available after one period of the adc?s conversion cycle (det ermined by the mod - ulator clock and the decimat ion ratio). the sinc3 filter results will be available after three periods of the adc?s conversion cycle. the ad0isel bit in regist er adc0cf determines when the end-of-conversion interrupt will occur, and return the adc to idle mode. if the ad0isel bit is set to ?1?, the ad0int bit will be set to ?1? when the fast filt er results are available. if the ad0isel bit is cleared to ?0?, the ad0int bit will be set to ?1? when the sinc3 filter re sults are available. the ad0sm bits will return to idle mode and the ad0busy bit will be cleared to ?0? when the selected filt er is finished. when using the sinc3 filter, a valid result will also be output by the fast filter. when using the fast f ilter in single-conve rsion mode, the sinc3 filter results will not be accurate. 5.3.2. continuous conversions continuous conversions are initiated by writing the adc system mode bits (ad0sm) to the ?continuous conversion? option. in continous co nversion mode, the adc will start a new conversion as soon as each conversion is completed. during the conversions, the ad0busy flag will be se t to ?1?. the fast filter results will be available after one period of the adc?s conversion cycle, and on every conversion cycle thereafter (determined by the modulator clock and the decimation ratio). the first sinc3 filter result will be available after three periods of the adc?s conversion cycle, and subsequent sinc3 conver sion results will be avail - able at the end of every conver sion cycle thereafter. the ad0isel bi t in register adc0cf determines when the end-of-con version interrupts will occur. if the ad0isel bit is cleared to ?0?, the ad0int bit will be set to ?1? when sinc3 filter results ar e available. if the ad0isel bit is set to ?1?, the ad0int bit will be set to ?1? when fast filter results are av ailable. regardless of the setting of the ad0isel bit, both filters will update their results registers when new results are ava ilable. to stop conversions and exit from continuous conversion mode, the ad0sm bits should be written to idle mode. 5.3.3. adc output the adc?s two filters each have their own output data registers. the sinc3 filter results are stored in the adc0h, adc0m, and adc0l registers, while the fast filter results are stored in the adc0fh, adc0fm, and adc0fl registers. the adc output can be configur ed for unipolar or bipolar mode using the ad0pol bit in register adc0cn. decoding of the adc output words are shown in table 5.1 and ta b l e 5.2 . the sinc3 filter uses information from the past three conv ersion cycles to produce an adc output. the fast fil - ter uses information from only the current conversion cycle to produce an adc output. the fast filter reacts more quickly to changes on the analog input, while the sinc3 filter produces lower-noise results.
table 5.1. adc0 unipolar output word coding (ad0pol = 0) *note: input voltage is voltage at adc inputs after amplification by the pga. table 5.2. adc0 bipolar output wo rd coding (ad0pol = 1) *note: input voltage is voltage at adc inpu ts after amplification by the pga. c8051f350/1/2/3 rev. 1.0 47 5.3.1. error conditions any errors during a conversion or calibration are indicated using bits in the adc0sta register. the ad0s3c flag will be set to ?1? if t here is a sinc3 filter clip during the conversion. likewise, the ad0ffc flag will be set to ?1? if there is a fast filter clip during the conversion. a filter clip occurs whenever an inter - nal filter register overflows during a conversion. the ad0ovr flag will be set to ?1? if an adc overrun con - dition occurs. an overrun occurs if the end of a conversion is reached wh ile the ad0int flag is still set to ?1? from the previous conversion. if the data registers have not been read, the new data values will be updated, and the previous conver sion will be lost. the general ad0err flag indicates that an ad0s3c, ad0ffc, or ad0ovr error condition has occurred, or that a calibration resulted in a value that was beyond the limits of the offset or gain register. the data output registers are u pdated at the end of every conversion regardless of whether or not an error occurs. 5.4. offset dac an 8-bit offset dac is included, which can be used fo r offset correction up to approximately 1/2 of the adc?s input range on any pga gain setting. the adc0dac register ( sfr definition 5.7 ) controls the off - set dac voltage. the register is decoded as a signed binary word. the msb (bit 7) determines the sign of the dac magnitude (0 = positive, 1 = negative), and the remaining seven bits (bits 6?0) determine the magnitude. each lsb of the offset dac is equivalen t to approximately 0.4% of the adc?s input span. a write to the adc0dac regist er initiates a change on the offset dac output. 5.5. burnout current sources the burnout current sources can be used to detect an open circuit or short circuit at the adc inputs. the burnout current sources are enabled by setting the ad0bce bit in register adc0cn to ?1? ( sfr definition 5.1 ). the positive-channel burnout current source sources approximately 2 a on ain+, and the negative- channel burnout current sinks approximately 2 a on ain?. if an open circ uit exists between ain+ and ain? when the burnout curr ent sources are enabled, the adc will read a full scale positive value. if a short-circuit exists between ain+ and ain? when the bu rnout current sources are enabled, the adc will input voltage* (ain+ ? ain?) 24-bit output word (c8051f350/1) 16-bit output word (c8051f352/3) vref ? 1 lsb 0xffffff 0xffff vref / 2 0x800000 0x8000 +1 lsb 0x000001 0x0001 0 0x000000 0x0000 input voltage* (ain+ ? ain?) 24-bit output word (c8051f350/1) 16-bit output word (c8051f352/3) vref ? 1 lsb 0x7fffff 0x7fff vref / 2 0x400000 0x4000 +1 lsb 0x000001 0x0001 0 0x000000 0x0000 ?1 lsb 0xffffff 0xffff ?vref / 2 0xc00000 0xc000 ?vref 0x800000 0x8000
c8051f350/1/2/3 48 rev. 1.0 read a value near zero. the burnout current sources should be disabled during normal adc measure - ments. sfr definition 5.1. adc0cn: adc0 control bits 7?5: unused: read = 000b, write = don?t care. bit 4: ad0pol: adc0 polarity. 0: adc operates in unipolar mode (straight binary result). 1: adc operates in bipolar mode (2's compliment result). bit 3: ad0bce: adc0 burnout current source enable. 0: adc burnout curr ent sources disabled. 1: adc burnout curr ent sources enabled. bits 2:0 ad0gn: adc0 programmable gain setting. 000: pga gain = 1. 001: pga gain = 2. 010: pga gain = 4. 011: pga gain = 8. 100: pga gain = 16. 101: pga gain = 32. 110: pga gain = 64. 111: pga gain = 128. this sfr can only be modified when adc0 is in idle mode. r r r r/w r/w r/w r/w r/w reset value ? ? ? ad0pol ad0bce ad0gn 00010000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf4
c8051f350/1/2/3 rev. 1.0 49 sfr definition 5.2. adc0cf: adc0 configuration bits 7?5: unused: read = 000b, write = don?t care. bit 4: ad0isel: adc0 inte rrupt source select. this bit selects which filter comple tion will set the ad0i nt interrupt flag. 0: sinc3 filter. 1: fast filter. bit 3: unused: read = 0b, write = don?t care. bit 2: ad0vref: adc0 vref source select. 0: adc0 uses the internal vref (2.5 v). settin g this bit to ?0? enable s the internal voltage reference. 1: adc0 uses an external vref. bits 1?0: unused: read = 00b, write = don?t care. this sfr can only be modified when adc0 is in idle mode. r r r r/w r r/w r r reset value ? ? ? ad0isel ? ad0vref ? ? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfb
c8051f350/1/2/3 50 rev. 1.0 sfr definition 5.3. adc0md: adc0 mode bit 7: ad0en: adc0 enable bit. 0: adc0 disabled. adc is in low-power shutdown. 1: adc0 enabled. adc is active and r eady to perform calibrations or conversions. note: disabling the adc automatically resets the ad0sm bits back to the "idle" state. bit 6: unused: read = 0b, write = don?t care. bits 5?4: reserved: must write to 00b. bit 3: unused: read = 0b, write = don?t care. bits 2?0: ad0sm: adc0 system mode select. these bits define the operating mode for the adc. they are used to initiate all adc conver- sion and calibration cycles. 000: idle 001: full internal calibra tion (offset and gain). 010: single conversion. 011: continuous conversion. 100: internal offset calibration. 101: internal gain calibration. 110: system offset calibration. 111: system gain calibration. note: any system mode change by the user during a conversion or calibration will terminate the operation, and co rrupt the result. to write to many of the other adc reg- isters, the ad0sm bits must be set to idle mode (000b). r/w r r/w r/w r r/w r/w r/w reset value ad0en ? reserved reserved ? ad0sm 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf3
c8051f350/1/2/3 rev. 1.0 51 sfr definition 5.4. adc0clk: adc0 modulat or clock divisor bits 7?0: adc0clk: adc0 modulator clock divisor. this register establishes the modulator clock (mdclk), by dividing down the system clock (sysclk). the input signal is sampled by th e modulator at a frequency of mdclk / 128. for optimal performance, the divider should be chosen such that the modulator clock is equal to 2.4576 mhz (modulator sampling rate = 19.2 khz). the system clock is divided according to the equation: mdclk = sysclk / (adc0clk + 1) note: the modulator sampling rate is not the adc output word rate. see section 5.1.4 for details. r/w r/w r/w r/w r/w r/w r/w r/w reset value adc0clk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf7 sfr definition 5.5. adc0dech: adc0 decimation ratio register high byte bits 7?3: unused: read = 00000b, write = don?t care. bits 2?0: deci[10:8]: adc0 decimation ratio register, bits 10?8. this register contains the high bits of the 11-bit adc decima tion ratio. the decimation ratio determines the output word rate of adc0, based on the modulator clock (mdclk). see the adc0decl register descripti on for more information. this sfr can only be modified when adc0 is in idle mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? deci10 deci9 deci8 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9b
c8051f350/1/2/3 52 rev. 1.0 sfr definition 5.6. adc0decl: adc0 decimation ratio register low byte bits 7?0: deci[7:0]: adc0 decimation ratio register, bits 7?0. this register contains the low byte of the 11 -bit adc decimation ratio. the decimation ratio determines the number of modulator input samples used to generate a single output word from the adc. the adc0 decimation ratio is defined as: decimation ratio = deci[10:0] + 1 the corresponding sampling period and output word rate of adc0 is: adc0 conversion period = [(deci[10:0] + 1) * 128] / mdclk adc0 output word rate = mdclk / [128 * (deci[10:0] + 1)] the minimum decimation ratio se tting is 20. any register sett ing below 19 will automatically be interpreted as 19. important: when using the fast filter, the decimation ratio must be divisible by 8 (deci[2:0] = 111b) . this sfr can only be modified when adc0 is in idle mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value deci7 deci6 deci5 deci4 deci3 deci2 deci1 deci0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9a sfr definition 5.7. adc0dac: adc0 offset dac bits 7?0: adc0dac: adc0 pga offset dac magnitude. this register determines the adc0 offset dac magnitude. the value in the offset dac is a signed-magnitude representation. bit 7 represen ts the sign value (0 = positive, 1 = nega- tive), while bits 6?0 represent the magnitude. this sfr can only be modified when adc0 is in idle mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value adc0dac 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbf
c8051f350/1/2/3 rev. 1.0 53 sfr definition 5.8. adc0buf: adc0 input buffer control bit 7: ad0bphe: positive channel high buffer enable. 0: positive channel high input buffer disabled. 1: positive channel high input buffer enabled. bit 6: ad0bple: positive channel low enable. 0: positive channel low input buffer disabled. 1: positive channel low input buffer enabled. bits 5?4: ad0bps: positive channel input selection. 00 = bypass input buffer (default). 01 = select low input buffer range. 10 = select high input buffer range. 11 = reserved. bit 3: ad0bnhe: negative channel high buffer enable. 0: negative channel high input buffer disabled. 1: negative channel high input buffer enabled. bit 2: ad0bnle: negative channel low enable. 0: negative channel low input buffer disabled. 1: negative channel low input buffer enabled. bits 1?0: ad0bns: negative channel input selection. 00 = bypass input buffer (default). 01 = select low input buffer range. 10 = select high input buffer range. 11 = reserved. this sfr can only be modified when adc0 is in idle mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0bphe ad0bple ad0bps ad0bnhe ad0bnle ad0bns 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbd
c8051f350/1/2/3 54 rev. 1.0 sfr definition 5.9. adc0sta: adc0 status bit 7: ad0busy: adc0 conversion in-progress flag. 0: adc0 is not performing conversions. 1: adc0 conversion in progress. bit 6: ad0cbsy: adc0 calib ration in-progress flag. 0: adc0 is not performing a calibration. 1: adc0 calibra tion in progress. bit 5: ad0int: adc0 conversion complete interrupt flag. this flag must be cleared in software. 0: adc0 has not completed a conversion si nce the last time this flag was cleared. 1: adc0 conversion is complete. bit 4: ad0s3c: adc0 sinc3 filter clip flag. this error flag indicates that a clip has occu rred in the sinc3 filter during the conversion process. 0: adc0 sinc3 filter clip did not occur. 1: adc0 sinc3 filter clip occurred during conversion. bit 3: ad0ffc: adc0 fast filter clip flag. this error flag indicates that a clip has occurred in the fast filter during the conversion pro- cess. 0: adc0 fast filter clip did not occur. 1: adc0 fast filter clip occurred during conversion. bit 2: ad0calc: adc0 calib ration complete flag. 0: adc0 calibrati on not complete. 1: adc0 calibration complete. bit 1: ad0err: adc0 error flag this bit is set by hardware under the following conditions: 1) a conversion cycle produced an ad0ovr, ad0s3c, or ad0ffc error. 2) a calibration cycle produced a result that is beyond the limits of the offset or gain register. 0: adc0 error did not occur. 1: adc0 error occurred. bit 0: ad0ovr: adc0 overrun flag this error flag indicates an overrun condition. 0: adc0 overrun did not occur. 1: adc0 overrun occurred. r r r/w r/w r/w r/w r/w r/w reset value ad0busy ad0cbsy ad0int ad0s3c ad0 ffc ad0calc ad0err ad0ovr 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xe8
c8051f350/1/2/3 rev. 1.0 55 sfr definition 5.10. adc0coh: adc0 offset calib ration register high byte bits 7?0: ocal[23:16]: adc0 offset calibration register high byte. this register contains the high byte of the 24-bit adc offset calibration value. r/w r/w r/w r/w r/w r/w r/w r/w reset value ocal23 ocal22 ocal21 ocal20 ocal19 ocal18 ocal17 ocal16 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbc sfr definition 5.11. adc0com: adc0 offset calibr ation register middle byte bits 7?0: ocal[15:8]: adc0 offset ca libration register middle byte. this register contains the middle byte of the 24-bit adc offset calibration value. r/w r/w r/w r/w r/w r/w r/w r/w reset value ocal15 ocal14 ocal13 ocal12 ocal11 ocal10 ocal9 ocal8 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbb sfr definition 5.12. adc0col: adc0 offset cali bration register low byte bits 7?0: ocal[7:0]: adc0 offset calibration register low byte. this register contains the low byte of the 24-bit adc offset calibration value. r/w r/w r/w r/w r/w r/w r/w r/w reset value ocal7 ocal6 ocal5 ocal4 ocal3 ocal2 ocal1 ocal0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xba
c8051f350/1/2/3 56 rev. 1.0 sfr definition 5.13. adc0cgh: adc0 gain calibration register high byte bits 7?0: gcal[23:16]: adc0 gain calibration register high byte. this register contains the high byte of the 24-bit adc gain calibration value. r/w r/w r/w r/w r/w r/w r/w r/w reset value gcal23 gcal22 gcal21 gcal20 gcal19 gcal18 gcal17 gcal16 variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10000000 sfr address: 0xad sfr definition 5.14. adc0cgm: adc0 gain calibr ation register middle byte bits 7?0: gcal[15:8]: adc0 gain ca libration register middle byte. this register contains the middle byte of the 24-bit adc gain calibration value. r/w r/w r/w r/w r/w r/w r/w r/w reset value gcal15 gcal14 gcal13 gcal12 gcal11 gcal10 gcal9 gcal8 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xac sfr definition 5.15. adc0cgl: adc0 gain calibration register low byte bits 7?0: gcal[7:0]: adc0 gain calibration register low byte. this register contains the low byte of the 24-bit adc gain calibration value. r/w r/w r/w r/w r/w r/w r/w r/w reset value gcal7 gcal6 gcal5 gcal4 gcal3 gcal2 gcal1 gcal0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xab
c8051f350/1/2/3 rev. 1.0 57 sfr definition 5.16. adc0h: adc0 conversion regist er (sinc3 filter) high byte bits 7?0: adc0h: adc0 conversion re gister (sinc3 filter) high byte. c8051f350/1 : this register contains bits 23?16 of the 24-bit adc sinc3 filter conversion result. c8051f352/3 : this register contains bits 15?8 of the 16-bit adc sinc3 filter conversion result. r/w r/w r/w r/w r/w r/w r/w r/w reset value adc0h 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc5 sfr definition 5.17. adc0m: adc0 conversion regist er (sinc3 filter) middle byte bits 7?0: adc0m: adc0 conversion re gister (sinc3 filter) middle byte. c8051f350/1 : this register contains bits 15?8 of the 24-bit adc sinc3 filter conversion result. c8051f352/3 : this register contains bits 7?0 of the 16-bit adc sinc3 filter conversion result. r/w r/w r/w r/w r/w r/w r/w r/w reset value adc0m 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc4 sfr definition 5.18. adc0l: adc0 conversion regi ster (sinc3 filter) low byte bits 7?0: adc0l: adc0 conversion re gister (sinc3 filter) low byte. c8051f350/1 : this register contains bits 7?0 of the 24-bit adc sinc3 filter conversion result. c8051f352/3 : this register contains all zeros (00000000b). r/w r/w r/w r/w r/w r/w r/w r/w reset value adc0l 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc3
c8051f350/1/2/3 58 rev. 1.0 sfr definition 5.19. adc0fh: adc0 conversion regist er (fast filter) high byte bits 7?0: adc0fh: adc0 conversion r egister (fast filter) high byte. c8051f350/1 : this register contains bits 23?16 of the 24-bit adc fast filter conversion result. c8051f352/3 : this register contains bits 15?8 of the 16-bit adc fast filter conversion result. r/w r/w r/w r/w r/w r/w r/w r/w reset value adc0fh 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfe sfr definition 5.20. adc0fm: adc0 conversi on register (fast filter) middle byte bits 7?0: adc0fm: adc0 conversion re gister (fast filter) middle byte. c8051f350/1 : this register contains bits 15?8 of the 24-bit adc fast filter conversion result. c8051f352/3 : this register contains bits 7?0 of the 16-bit adc fast filter conversion result. r/w r/w r/w r/w r/w r/w r/w r/w reset value adc0fm 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfd sfr definition 5.21. adc0fl: adc0 conversion regi ster (fast filter) low byte bits 7?0: adc0fl: adc0 conversion register (fast filter) low byte. c8051f350/1 : this register contains bits 7?0 of the 24-bit adc fast filter conversion result. c8051f352/3 : this register contains all zeros (00000000b). r/w r/w r/w r/w r/w r/w r/w r/w reset value adc0fl 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfc
c8051f350/1/2/3 rev. 1.0 59 5.6. analog multiplexer adc0 includes analog multiplexer circuitry with independent selection capability for the ain+ and ain? inputs. each input can be connected to one of ten po ssible input source s: ain0.0 though ain0.7, agnd, or the on-chip temperature sensor circuitry ( figure 5.5 ). the adc0mux register ( sfr definition 5.22 ) con - trols the input mux selection for both input channels. the multiplexer configuration allows for measurement of single-ended or differential signals. a single- ended measurement can be performed by connecting one of the adc inputs to agnd. additionally, the temperature sensor can be measured in single-ended or dif - ferential mode. the temperature sensor is automatica lly enabled when it is se lected with the adc multi - plexer. see section ?8. temperature sensor? on page 77 for more details on the temperature sensor. adc0mux ad0psel3 ad0psel2 ad0psel1 ad0psel0 ad0nsel3 ad0nsel2 ad0nsel1 ad0nsel0 ain0.0 ain0.1 ain0.2 ain0.3 ain0.4 ain0.5 ain0.6 ain0.7 agnd ain0.0 ain0.1 ain0.2 ain0.3 ain0.4 ain0.5 ain0.6 ain0.7 agnd temperature sensor temp- temp+ adc0 ain+ ain- figure 5.5. adc0 mu ltiplexer connections
c8051f350/1/2/3 60 rev. 1.0 sfr definition 5.22. adc0mux: adc0 analog multiplexer control bits 7?4: ad0psel: adc0 positive multiplexer c hannel select. 0000 = ain0.0 0001 = ain0.1 0010 = ain0.2 0011 = ain0.3 0100 = ain0.4 0101 = ain0.5 0110 = ain0.6 0111 = ain0.7 1111 = temperature sensor all other settings = agnd bits 3?0: ad0nsel: adc0 negative multiplexer channel select. 0000 = ain0.0 0001 = ain0.1 0010 = ain0.2 0011 = ain0.3 0100 = ain0.4 0101 = ain0.5 0110 = ain0.6 0111 = ain0.7 1111 = temperature sensor all other settings = agnd this sfr should only be modified when adc0 is in idle mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0psel ad0nsel 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc6
c8051f350/1/2/3 rev. 1.0 61 table 5.3. adc0 electrical characteristics v dd = av+ = 3.0 v, vref = 2.5 v external , pga gain = 1, mdclk = 2.4576 mhz, decimation ratio = 1920, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units 24-bit adc (c8051f350/1) resolution 24 bits no missing codes 24 bits 16-bit adc (c8051f352/3) resolution 16 bits no missing codes 16 bits all devices integral nonlinearity 15 ppm fs offset error (calibrated) 5 ppm offset drift vs. temperature 10 nv/ c gain error (calibrated) 0.002 % gain drift vs. temperature 0.5 ppm/ c modulator clock (mdclk) 2.4576 mhz modulator sampling frequency mdclk/128 hz output word rate 1000 sps analog inputs analog input voltage range (ain+ ? ain?) pga gain = 1, bipolar pga gain = 1, unipolar ?vref 0 +vref +vref v absolute voltage on ain+ or ain? pin with respect to agnd input buffers off 0 av+ v input current input buffer on 0.5 na input impedance input buffer off, gain = 1 7 m ? common mode rejection ratio dc 50/60 hz 95 110 100 db db input buffers high buffer input range with respect to agnd pga gain = 1, 2, 4, or 8 pga gain = 16 pga gain = 32 pga gain = 64 or 128 1.4 1.45 1.5 1.6 av+ ? 0.1 av+ ? 0.15 av+ ? 0.2 av+ ? 0.25 v v v v low buffer input range with respect to agnd pga gain = 1, 2, 4, or 8 pga gain = 16 pga gain = 32 pga gain = 64 or 128 0.1 0.15 0.2 0.25 av+ ? 1.4 av+ ? 1.45 av+ ? 1.5 av+ ? 1.6 v v v v burnout current sources
c8051f350/1/2/3 62 rev. 1.0 table 5.4. adc0 sinc3 filter ty pical rms noise (v) decimation ratio output word rate* pga gain setting 1 2 4 8 16 32 64 128 1920 10 hz 2.38 1.23 0.68 0.41 0.24 0.16 0.12 0.11 768 25 hz 3.90 2.04 1.14 0.68 0.44 0.33 0.28 0.27 640 30 hz 4.50 2.39 1.31 0.81 0.54 0.42 0.36 0.36 384 50 hz 6.00 3.21 1.86 1.20 0.86 0.73 0.66 0.66 320 60 hz 7.26 3.96 2.32 1.51 1.11 0.97 0.89 0.89 192 100 hz 13.1 7.11 4.24 2.85 2.16 1.91 1.79 1.77 80 240 hz 93.2 47.7 24.8 13.9 9.34 7.61 6.97 6.67 40 480 hz 537 267 135 69.5 38.8 25.7 20.9 18.9 20 960 hz 2974 1586 771 379 196 108 70.0 45.4 *note: output word rate assuming modulator clock frequency = 2.4576 mhz
table 5.5. adc0 sinc3 filter ef fective resolution 1 in unipolar mode (bits) decimation ratio output word rate 2 pga gain setting 1 2 4 8 16 32 64 128 1920 10 hz 20.00 19.95 19.81 19.54 19.31 18.90 18.31 17.44 768 25 hz 19.29 19.22 19.06 18.81 18.44 17.85 17.09 16.14 640 30 hz 19.08 19.00 18.86 18.56 18.14 17.51 16.73 15.73 384 50 hz 18.67 18.57 18.36 17.99 17.47 16.71 15.85 14.85 320 60 hz 18.39 18.27 18.04 17.66 17.10 16.30 15.42 14.42 192 100 hz 17.54 17.42 17.17 16.74 16.14 15.32 14.41 13.43 80 240 hz 14.71 14.68 14.62 14.46 14.03 13.33 12.45 11.52 40 480 hz 12.18 12.19 12.18 12.13 11.98 11.57 10.87 10.01 20 960 hz 9.72 9.62 9.66 9.69 9.64 9.50 9.12 8.75 notes: 1. effective resolution = log 2 fullinputrange v () rms noise v () --------------------------------------------------- ?? ?? full input range = v ref pga gain --------------------------- in unipolar mode and rms noise is obtained from ta b l e 5.4 . 2. output word rate assuming modular clock frequency = 2.4576 mhz flicker-free (noise-free) resolution = log 2 fullinputrange v () 6.6 rms noise v () --------------------------------------------------- - ?? ?? full input range = v ref pga gain --------------------------- in unipolar mode and rms noise is obtained from ta b l e 5.4 . 2. output word rate assuming modular clock frequency = 2.4576 mhz (sampling clock frequency = 19.2 khz) c8051f350/1/2/3 rev. 1.0 63
table 5.7. adc0 fast filter ty pical rms noise (v) decimation ratio output word rate* pga gain setting 1 2 4 8 16 32 64 128 1920 10 hz 4.84 2.68 1.55 1.03 0.75 0.61 0.56 0.58 768 25 hz 17.92 9.77 5.85 3.72 2.79 2.45 2.28 2.21 640 30 hz 29.98 14.84 7.81 5.39 3.89 3.27 3.19 3.03 384 50 hz 103.93 48.53 25.71 14.07 9.24 7.17 6.45 6.06 320 60 hz 171.12 89.87 42.99 23.05 13.81 10.33 9.00 8.52 192 100 hz 550.29 305.55 140.58 72.90 40.97 25.52 19.96 17.68 *note: output word rate assuming modulator clock frequency = 2.4576 mhz effective resolution = log 2 fullinputrange v () rms noise v () --------------------------------------------------- ?? ?? full input range = v ref pga gain --------------------------- in unipolar mode and rms noise is obtained from ta b l e 5.7 . 2. output word rate assuming modular clock frequency = 2.4576 mhz (sampling clock frequency = 19.2 khz) c8051f350/1/2/3 64 rev. 1.0
table 5.9. adc0 fast filter flicker-f ree (noise-free) resolution 1 in unipolar mode (bits) decimation ratio output word rate 2 pga gain setting 1 2 4 8 16 32 64 128 1920 10 hz 16.26 16.11 15.90 15.49 14.95 14.24 13.37 12.32 768 25 hz 14.37 14.24 13.98 13.64 13.05 12.24 11.34 10.39 640 30 hz 13.63 13.64 13.57 13.10 12.57 11.82 10.86 9.93 384 50 hz 11.83 11.93 11.85 11.72 11.32 10.69 9.84 8.93 320 60 hz 11.11 11.04 11.11 11.00 10.74 10.16 9.36 8.44 192 100 hz 9.43 9.28 9.40 9.34 9.17 8.86 8.21 7.39 notes: 1. flicker-free (noise-free) resolution = log 2 fullinputrange v () 6.6 rms noise v () --------------------------------------------------- - ?? ?? full input range = v ref pga gain --------------------------- in unipolar mode and rms noise is obtained from ta b l e 5.7 . 2. output word rate assuming modular clock frequency = 2.4576 mhz (sampling clock frequency = 19.2 khz) c8051f350/1/2/3 rev. 1.0 65
c8051f350/1/2/3 66 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 67 6. 8-bit current mode dacs (ida0 and ida1) the c8051f350/1/2/3 devices include two 8-bit curr ent-mode digital-to-analog converters (idacs). the maximum current output of the idacs can be adjusted for four different current settings; 0.25 ma, 0.5 ma, 1 ma, and 2 ma. the idacs can be individually enabled or disabled using the enable bits in the corre - sponding idac control register (ida0cn or ida1cn). an internal bandgap bias generator is used to gen - erate a reference current for the idacs whenever th ey are enabled. idac updates can be performed on- demand, scheduled on a timer overflow, or synchronized with an external pin edge. figure 6.1 shows a block diagram of the idac circuitry. idan 8 idan output idancn idanen idancm2 idancm1 idancm0 idancsc idanomd1 idanomd0 idan latch 8 idan timer 0 timer 1 timer 2 timer 3 cnvstr figure 6.1. idac functional block diagram
c8051f350/1/2/3 68 rev. 1.0 6.1. idac output scheduling a flexible output update mechanism allows for seam less full-scale changes and supports jitter-free updates for waveform generation. three update modes are provided, allowing idac output updates on a write to the idac?s data register, on a timer overflow, or on an external pin edge. 6.1.1. update output on-demand in its default mode (idancn.[6:4] = ?111?) the idac output is updated ?on-demand? with a write to the data register (idan). in this mode, data is immediately latc hed into the idac after a write to its data register. 6.1.2. update output based on timer overflow the idac output update can be scheduled on a timer ov erflow. this feature is useful in systems where the idac is used to generate a waveform of a defined sampling rate, by eliminating the effects of variable interrupt latency and instruction execution on the timing of the idac output. when the idancm bits (idancn.[6:4]) are set to ?000?, ?001?, ?0 10? or ?011?, writes to the idac data register (idan) are held until an associated timer overflow event (timer 0, timer 1, timer 2 or timer 3, respectively) occurs, at which time the data register contents are copied to the idac in put latch, allowing the idac output to change to the new value. 6.1.3. update output based on cnvstr edge the idac output can also be configured to update on a rising edge, falling edge, or both edges of the external cnvstr signal. when the idancm bits (idancn.[6:4]) are set to ?100?, ?101?, or ?110?, writes to the idac data register (idan) are held until an edge occurs on the cnvstr input pin. the particular set - ting of the idancm bits determines whether the idac ou tput is updated on rising, falling, or both edges of cnvstr. when a corresponding edge occurs, the data register contents are copied to the idac input latch, allowing the idac output to change to the new value. 6.2. idac output mapping the data word mapping for the idac is shown in figure 6.2. the full-scale output current of the idac is selected using the idanomd bits (idanc n[1:0]). by default, the idac is se t to a full-scale output current of 0.25 ma. the idanomd bits can also be configured to provide full-scale output currents of 0.5 ma, 1 ma, or 2 ma. idan data word (d7 ? d0) output current vs idanomd bit setting ?11? (2 ma) ?10? (1 ma) ?01? (0.5 ma) ?00? (0.25 ma) 0x00 0 ma 0 ma 0 ma 0 ma 0x01 1/256 x 2 ma 1/256 x 1 ma 1/256 x 0.5 ma 1/256 x 0.25 ma 0x80 128/256 x 2 ma 128/256 x 1 ma 128/256 x 0.5 ma 128/256 x 0.25 ma 0xff 255/256 x 2 ma 255/256 x 1 ma 255/256 x 0.5 ma 255/256 x 0.25 ma figure 6.2. idac data word mapping
c8051f350/1/2/3 rev. 1.0 69 sfr definition 6.1. ida0cn: ida0 control bit 7: ida0en: ida0 enable. 0: ida0 disabled. 1: ida0 enabled. bits 6?4: ida0cm[2:0]: ida0 update source select bits. 000: dac output updates on timer 0 overflow. 001: dac output updates on timer 1 overflow. 010: dac output updates on timer 2 overflow. 011: dac output updates on timer 3 overflow. 100: dac output updates on rising edge of cnvstr. 101: dac output updates on falling edge of cnvstr. 110: dac output updates on any edge of cnvstr. 111: dac output updates on write to ida0. bit 3: ida0csc: ida0 constant supply current. 0: current draw on v dd is dependent on ida0 output word. 1: current draw on v dd is independent of ida0 output word. bit 2: unused. read = 0b, write = don?t care. bits 1:0: ida0omd[1:0]: ida0 output mode select bits. 00: 0.25 ma full-scale output current. 01: 0.5 ma full-scale output current. 10: 1.0 ma full-scale output current. 11: 2.0 ma full-scale output current. r/w r/w r/w r/w r/w r r/w r/w reset value ida0en ida0cm ida0csc ? ida0omd 01110000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb9 sfr definition 6.2. ida0: ida0 data word bits 7?0: ida0 data word bits. bits 7?0 hold the 8-bit ida0 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x96
c8051f350/1/2/3 70 rev. 1.0 sfr definition 6.3. ida1cn: ida1 control bit 7: ida1en: ida1 enable. 0: ida1 disabled. 1: ida1 enabled. bits 6?4: ida1cm[2:0]: ida1 update source select bits. 000: dac output updates on timer 0 overflow. 001: dac output updates on timer 1 overflow. 010: dac output updates on timer 2 overflow. 011: dac output updates on timer 3 overflow. 100: dac output updates on rising edge of cnvstr. 101: dac output updates on falling edge of cnvstr. 110: dac output updates on any edge of cnvstr. 111: dac output updates on write to ida1. bit 3: ida1csc: ida1 constant supply current. 0: current draw on v dd is dependent on ida1 output word. 1: current draw on v dd is independent of ida1 output word. bit 2: unused. read = 0b, write = don?t care. bits 1:0: ida1omd[1:0]: ida1 output mode select bits. 00: 0.25 ma full-scale output current. 01: 0.5 ma full-scale output current. 10: 1.0 ma full-scale output current. 11: 2.0 ma full-scale output current. r/w r/w r/w r/w r/w r r/w r/w reset value ida1en ida1cm ida1csc ? ida1omd 01110000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd7 sfr definition 6.4. ida1: ida1 data word bits 7?0: ida1 data word bits. bits 7?0 hold the 8-bit ida1 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xdd
c8051f350/1/2/3 rev. 1.0 71 6.3. idac external pin connections the ida0 output is connected to p1.6, and the ida1 output is connected to p1.7. when the enable bit for an idac (idanen) is set to ?0?, the idac output behav es as a normal gpio pin. when the enable bit is set to ?1?, the digital output drivers and weak pull-up for the idac pin are automatically disabled, and the pin is connected to the idac output. when using the idacs, th e idac pins should be skipped in the crossbar by setting the corresponding pnskip bits to a ?1?. figure 6.3 shows the pin connections for ida0 and ida1. ida0 p1.6 0 1 ida0en ida1 p1.7 0 1 ida1en figure 6.3. idac pin connections
c8051f350/1/2/3 72 rev. 1.0 . table 6.1. idac electrical characteristics ?40 to +85 c, v dd = 3.0 v full-scale output current set to 2 ma unless otherwise specified. parameter conditions min typ max units static performance resolution 8 bits integral nonlinearity 0.5 lsb differential nonlinearity guaranteed monotonic 0.5 1 lsb output compliance range v dd ? 1.2 v output noise i out = 2 ma; r load = 100 ?
c8051f350/1/2/3 rev. 1.0 73 7. voltage reference there are two voltage reference options for the c8051f350/1/2/3 adcs: the internal 2.5 v reference volt - age, or an external reference voltage (see figure 7.1 ). the ad0vref bit in the adc0cf register selects the reference source. the internal voltage reference circuit consists of a 1.25 v, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier, to produce a 2.5 v voltage reference. when the inter - nal voltage reference is used, it is driven out on the vref+ pin, and the vref? pin is connected to agnd. the internal voltage reference is enabled by setting th e ad0en bit in register adc0md to ?1? and clearing the ad0vref bit in register adc0cf to ?0? (see section ?5. 24 or 16-bit analog to digital converter (adc0)? on page 41 ). electrical specifications for the inter nal voltage reference and bias generators are given in table 7.1 . the internal oscillator bias generator is aut omatically enabled whenever the internal oscillator is enabled. for power requirement charac terization, the biase bit in register ref0 cn can also be us ed to enable the internal oscillator bias generator, when the oscillator itself is not enabled. likewise, th e refbe bit in regis - ter ref0cn can be used to enable the internal bandgap generator, which is used by the adc, the idacs, the clock multiplier, and the internal voltage reference. the internal reference bias generator is automati - cally enabled whenever a peripheral requires it. see sfr definition 7.1 for the ref0cn register descrip - tion. vref+ internal reference bias generator to adc, idacs, clock multiplier ad0en ida0en ida1en mulen ref0cn biase refbe vref- 2.5v reference buffer en internal oscillator bias generator to internal oscillator en ioscen ad0en ad0vref en vref to adc external voltage reference (optional) + bypass capacitors (recommended) agnd figure 7.1. reference circuitry block diagram
c8051f350/1/2/3 74 rev. 1.0 sfr definition 7.1. ref0cn: reference control note: modification of this register is not necessar y in most applications. the appropriate circuitry is enabled when it is needed by a peripheral. bits7?2: unused. read = 000000b; write = don?t care. bit1: biase: internal o scillator bias enable. this bit is ored with the internal oscillator enable bit to en able the internal oscillator bias generator. 0: internal oscillator bias enable determ ined by internal oscillator enable bit. 1: internal oscillato r bias generator on. bit0: refbe: internal reference bias enable bit. this bit is ored with the enable bits for adc0 , idac0, idac1, and the clock multiplier to enable the internal bandgap generator. 0: internal reference bias enable determined by individual component. 1: internal reference bias enabled. r r r r r r r/w r/w reset value ? ? ? ? ? ? biase refbe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd1
table 7.1. voltage reference electrical characteristics v dd = 3.0 v; ?40 to +85 c unless otherwise specified parameter conditions min typ max units internal reference output voltage 25c ambient 2.45 v vref short-circuit current to a g n d to av + 9 20 ma a vref temperature coefficient 15 ppm/c load regulation load = 0 to 200 a to agnd 0.5 ppm/a vref turn-on time 1 (0.01%) 4.7 f tantalum, 0.1 f ceramic bypass capacitors 3.9 ms vref turn-on time 2 (0.01%) 0.1f ceramic bypass capacitor 400 s vref turn-on time 3 (0.01%) no bypass capacitor 3 s power supply rejection 50 db external reference input voltage range (vref+ ? vref?) 1 2.5 av+ v voltage on vref+ or vref? pin with respect to agnd 0 av+ v input current vref = 2.5 v 2 a common mode rejection ratio 120 db power specifications internal oscillator bias generator a internal reference bias genera - tor 42 a band gap generator 70 a c8051f350/1/2/3 rev. 1.0 75
c8051f350/1/2/3 76 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 77 8. temperature sensor the temperature sensor system consists of two diodes with different temperature properties and two con - stant current sources. the two channels are connect ed to the adc inputs internally, using the adc?s ana - log multiplexer. the temperature sensor system ca n be used in single-ended or differential mode to measure the temperature of the c 8051f350/1/2/3. single channel measurements produce more output voltage per degree c, but are not as linear as differential measurements. see ta b l e 8.1 for temperature sensor electrical characteristics. the temperature sensor channels are automatically enabled when they are selected by the adc multi - plexer. to use the temperature sensor for a single -channel measurement, the adc multiplexer should be configured with one channel connected to the temper ature sensor, and the othe r connected to agnd. for a differential measurement, the temperature sensor should be selected for both adc channels. the transfer functions for single-channel and differential measurements are shown in figure 8.2 and figure 8.3 , respectively. for slope and offset values, refer to ta b l e 8.1 . av+ agnd to ain+ mux to ain- mux ain+ channel ain- channel figure 8.1. temperature sensor block diagram table 8.1. temperature sensor electrical characteristics v dd = 3.0 v; ?40 to +85 c unless otherwise specified parameter conditions min typ max units linearity single channel measurement differential measurement 0.4 0.01 c c offset ain+ channel measurement, temp = 0 c differential measurement, temp = 0 c 757 54.3 mv mv offset error* 1 mv slope ain+ channel measurement differential measurement ?1.73 205 mv/c uv/c slope error* 6.6 v/c av+ supply current single channel measurement differential measurement 10 20 a a *note: represents one standard deviation from the mean.
0 -50 50 100 temperature (celsius) voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope 0 -50 50 100 temperature (celsius) voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope c8051f350/1/2/3 78 rev. 1.0 figure 8.2. single cha nnel transfer function figure 8.3. differenti al transfer function
c8051f350/1/2/3 rev. 1.0 79 9. comparator0 c8051f350/1/2/3 devices include an on-chip programmable voltage comparator, comparator0, shown in figure 9.1 . the comparator offers programmable response time and hysteresis and two ou tputs that are optionally available at the port pins: a synchronous ?latched? ou tput (cp0), or an asynchronous ?raw? output (cp0a). the asynchronous cp0a signal is available even wh en the system clock is not active. this allows the comparator to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator output may be confi gured as open drain or push-pull (see section ?18.2. port i/o ini - tialization? on page 141 ). comparator0 may also be used as a reset source (see section ?14.5. comparator0 reset? on page 118 ). vdd cpt0cn reset decision tree + - q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea cp0 (synchronous output) cp0a (asynchronous output) figure 9.1. comparator0 functional block diagram the comparator output can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, the comp arator output is available asynch ronous or synchronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis - abled, the comparator output (if assigned to a port i/o pin) defaults to the logic low state, and its supply current falls to less than 100 na. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparat or electrical specifications are given in ta b l e 9.1 . the comparator response time may be configured in software via the cpt0md register (see sfr defini - tion 9.2 ). selecting a longer response time reduces the comparator supply current. see ta b l e 9.1 for com - plete timing and power cons umption specifications.
positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol c8051f350/1/2/3 80 rev. 1.0 figure 9.2. compar ator hysteresis plot the comparator hysteresis is software-programmabl e via its comparator control register cpt0cn. the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hyst eresis around the threshold voltage. the comparator hysteresis is programmed using bits3?0 in the comparator control register cpt0cn (shown in sfr definition 9.1 ). the amount of negative hysteresis vo ltage is determined by the settings of the cp0hyn bits. as shown in figure 9.2 , settings of 20, 10 or 5 mv of negative hysteresis can be pro - grammed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cp0hyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter - rupt enable and priority control, see section ?12. interrupt handler? on page 105 ). the cp0fif flag is set to logic 1 upon a comparator falling-e dge occurrence, and the cp0r if flag is set to logic 1 upon the comparator rising-edge occurrence. once set, these bits remain set until cleared by software. the com - parator rising-edge interrupt mask is enabled by setting cp0rie to a logic 1. the comparat or0 falling-edge interrupt mask is enabled by setting cp0fie to a logic 1. the output state of the comparator can be obtained at any time by reading the cp0out bit. the compar - ator is enabled by setting the cp0en bit to logic 1, and is disabled by clearing this bit to logic 0. note that false rising ed ges and falling edges can be detected when the comparator is fi rst powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. this power up time is specified in ta b l e 9.1 on page 85 .
c8051f350/1/2/3 rev. 1.0 81 sfr definition 9.1. cpt0cn: comparator0 control bit7: cp0en: comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. bit6: cp0out: comparator0 output state flag. 0: voltage on cp0+ < cp0?. 1: voltage on cp0+ > cp0?. bit5: cp0rif: comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occurr ed since this flag was last cleared. 1: comparator0 rising edge has occurred. bit4: cp0fif: comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-e dge has occurred since this flag was last cleared. 1: comparator0 falling-edge has occurred. bits3?2: cp0hyp1?0: comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1?0: cp0hyn1?0: comparator0 nega tive hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. r/w r r/w r/w r/w r/w r/w r/w reset value cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9c
c8051f350/1/2/3 82 rev. 1.0 sfr definition 9.2. cpt0md: comparator 0 mode selection bits7?6: unused. read = 00b, write = don?t care. bit5: cp0rie: comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. bit4: cp0fie: comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge interrupt disabled. 1: comparator0 falling-edge interrupt enabled. bits3?2: unused. read = 00b, write = don?t care. bits1?0: cp0md1?cp0md0: comparator0 mode select these bits select the response time for comparator0. r r r/w r/w r r r/w r/w reset value ? ? cp0rie cp0fie ? ? cp0md1 cp0md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9d mode cp0md1 cp0md0 notes 0 0 0 fastest response time 101 ? 210 ? 311 lowest power consump- tion
c8051f350/1/2/3 rev. 1.0 83 9.1. comparator0 inputs and outputs figure 9.3 shows the external pin connections for the comp arator. the positive and negative inputs to the comparator can each be routed to one of eight different pins using the comparator mux. comparator out - puts can optionally be routed to port pins using the crossbar circuitry. the comparator inputs (cp0+ and cp0?) are selected in the cpt0mx register (sfr definition 9.3). the cmx0p1?cmx0p0 bits select the comparator?s positi ve input; the cmx0n1?cmx0n0 bits select the com - parator?s negative input. important note about comparator inputs: the port pins selected as compara - tor inputs should be configured as analog inputs in their associated port co nfiguration register, and configured to be skipped by the crossbar. two versions of the comparator output can be routed to port pins, using the port i/o crossbar. the raw (asynchronous) comparat or output cp0a is enabled using bit 5 in the xbr0 register, and will be available at p1.2. the cp0 output (synchronize d to sysclk) is available at p1.3 wh en it is enabled with bit 4 in the xbr0 register. vdd + - q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cp0 cp0a p1.5 p1.4 0 1 0 1 xbr0 cp0e cp0ae p0.0 p0.2 p0.4 p0.6 p0.1 p0.3 p0.5 p0.7 p1.0 p1.2 p1.4 p1.6 p1.1 p1.3 p1.5 p1.7 cpt0mx cmx0n3 cmx0n2 cmx0n1 cmx0n0 cmx0p3 cmx0p2 cmx0p1 cmx0p0 figure 9.3. comparat or pin connections
c8051f350/1/2/3 84 rev. 1.0 sfr definition 9.3. cpt0mx: comparator0 mux selection bits7?4: cmx0n2?cmx0n0: comparat or0 negative input mux select. these bits select which port pin is us ed as the comparator0 negative input. bits3?0: cmx0p2?cmx0p0: comparator0 positive input mux select. these bits select which port pin is us ed as the comparator0 positive input. r/w r/w r/w r/w r/w r/w r/w r/w reset value cmx0n3 cmx0n2 cmx0n1 cmx0n0 cmx0p3 cmx0p2 cmx0p1 cmx0p0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9f cmx0n3 cmx0n2 cmx0n1 cmx0n0 negative input 0000 p0.1 0001 p0.3 0010 p0.5 0011 p0.7 0100 p1.1 0101 p1.3 0110 p1.5 0111 p1.7 1xxx none cmx0p3 cmx0p2 cmx0p1 cmx0p0 positive input 0000 p0.0 0001 p0.2 0010 p0.4 0011 p0.6 0100 p1.0 0101 p1.2 0110 p1.4 0111 p1.6 1xxx none
table 9.1. comparator electrical characteristics vdd = 3.0 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm* = 1.5 v cp0+ ? cp0? = 100 mv 100 ns cp0+ ? cp0? = ?100 mv 250 ns response time: mode 1, vcm* = 1.5 v cp0+ ? cp0? = 100 mv 175 ns cp0+ ? cp0? = ?100 mv 500 ns response time: mode 2, vcm* = 1.5 v cp0+ ? cp0? = 100 mv 320 ns cp0+ ? cp0? = ?100 mv 1100 ns response time: mode 3, vcm* = 1.5 v cp0+ ? cp0? = 100 mv 1050 ns cp0+ ? cp0? = ?100 mv 5200 ns common-mode rejection ratio 1.5 4 mv/v positive hysteresis 1 cp0hyp1-0 = 00 0 1 mv positive hysteresis 2 cp0hyp1-0 = 01 2 5 10 mv positive hysteresis 3 cp0hyp1-0 = 10 7 10 20 mv positive hysteresis 4 cp0hyp1-0 = 11 15 20 30 mv negative hysteresis 1 cp0hyn1-0 = 00 0 1 mv negative hysteresis 2 cp0hyn1-0 = 01 2 5 10 mv negative hysteresis 3 cp0hyn1-0 = 10 7 10 20 mv negative hysteresis 4 cp0hyn1-0 = 11 15 20 30 mv inverting or non-inverting input voltage range ?0.25 vdd + 0.25 v input capacitance 4 pf input bias current 0.001 na input offset voltage ?5 +5 mv power supply power supply rejection 0.1 mv/v power-up time 10 s supply current at dc mode 0 7.6 a mode 1 3.2 a mode 2 1.3 a mode 3 0.4 a *note: vcm is the common-mode voltage on cp0+ and cp0?. c8051f350/1/2/3 rev. 1.0 85
c8051f350/1/2/3 86 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 87 10. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set. standard 803x/805x assemblers and compilers can be used to develop soft - ware. the c8051f35x family has a superset of all the peripherals included with a standard 8051. see sec - tion ? 1. system overview ? on page 17 for more information about the available peripherals. the cip-51 includes on-chip debug hardware which interfaces di rectly with the analog and digital subsystems, provid - ing a complete data acquisition or control-system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and f unctions to extend its capability (see figure 10.1 for a block diagram). the cip-51 core includes the following features: - fully compatible with mcs-51 instruction set - 50 mips peak throughput - 256 bytes of internal ram - extended interrupt handler - reset input - power management modes - integrated debug logic data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8 figure 10.1. cip-51 block diagram
c8051f350/1/2/3 88 rev. 1.0 performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's syst em clock running at 50 mhz, it has a peak throughput of 50 mips. the cip-51 has a total of 109 instructions. the table below shows the tota l number of instructions th at require each execution time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the cygnal 2-wire (c2) inte rface. note that the re-programmable flash can also be read and changed a single byte at a time by the application software using the movc and movx instructions. this feature allows program memory to be used for non-volatile data storage as well as updat - ing program code under software control. the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem - ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or other on-chip resources. the cip-51 is support ed by development tools from silicon labs and third party vendors. silicon labs pro - vides an integrated development environment (ide) in cluding editor, macro assembler, debugger and pro - grammer. the ide's debugger and programmer interface to the cip-51 via the on-chip debug logic to provide fast and efficient in-system device program ming and debugging. third party macro assemblers and c compilers are also available.
c8051f350/1/2/3 rev. 1.0 89 10.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc - tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan - dard 8051. 10.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not take n as opposed to when the branch is taken. ta b l e 10.1 is the cip-51 instruction set summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 10.1.2. movx instruction and program memory the movx instruction is typically used to access data stored in xdata memory space. in the cip-51, the movx instruction can also be used to write or erase on-chip program memory space implemented as re- programmable flash memory. the flas h access feature provides a mechanism for the cip-51 to update program code and use the program memory space for non-volatile data storage. refer to section ?15. flash memory? on page 121 for further details. table 10.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1
c8051f350/1/2/3 90 rev. 1.0 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 table 10.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
c8051f350/1/2/3 rev. 1.0 91 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 table 10.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
c8051f350/1/2/3 92 rev. 1.0 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not equal 3 3/4 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 notes on registers, operands and addressing modes: rn - register r0?r7 of the curr ently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. table 10.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
c8051f350/1/2/3 rev. 1.0 93 10.2. register descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic l. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sections of the datasheet associated with their corresponding sys - tem function. sfr definition 10.1. sp: stack pointer bits7?0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp r egister defaults to 0x07 after reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x81 sfr definition 10.2. dpl: data pointer low byte bits7?0: dpl: data pointer low. the dpl register is the low byte of the 16-b it dptr. dptr is used to access indirectly addressed xram and flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x82 sfr definition 10.3. dph: data pointer high byte bits7?0: dph: data pointer high. the dph register is the high byte of the 16-b it dptr. dptr is used to access indirectly addressed xram and flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x83
c8051f350/1/2/3 94 rev. 1.0 sfr definition 10.4. psw: program status word bit7: cy: carry flag. this bit is set when the last arithmetic operat ion resulted in a carry (addition) or a borrow (subtraction). it is cleared to 0 by all other arithmetic operations. bit6: ac: auxiliary carry flag this bit is set when the last arithmetic operati on resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to 0 by all other arithmetic operations. bit5: f0: user flag 0. this is a bit-addressable, general purpose flag for use under software control. bits4?3: rs1?rs0: register bank select. these bits select which register ban k is used during register accesses.
c8051f350/1/2/3 rev. 1.0 95 sfr definition 10.5. acc: accumulator bits7?0: acc: accumulator. this register is the accumulator for arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xe0 sfr definition 10.6. b: b register bits7?0: b: b register. this register serves as a second accumu lator for certain arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xf0
c8051f350/1/2/3 96 rev. 1.0 10.3. power management modes the cip-51 core has two software programmable power management modes: idle and stop. idle mode halts the cpu while leaving the peripherals and internal clocks active. in stop mode, the cpu is halted, all interrupts and timers (excep t the missing clock detector) are inactive, and the internal os cillator is stopped (analog peripherals remain in their selected states; the external osc illator is not effected ). since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode consumes the least power. sfr defini - tion 10.7 describes the power control register (pcon) used to control the cip-51's power management modes. although the cip-51 has idle and stop modes built in (as with any standard 8051 architecture), power management of the entire mcu is better accomplished by enabling/disabling individual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw littl e power when they are not in use. turning off the oscil - lators lowers power consumption considerably; however a reset is required to restart the mcu. 10.3.1. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes executio n. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset and thereby termi - nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, th e wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro - vides the opportunity for additional power savings, allo wing the system to remain in the idle mode indefi - nitely, waiting for an external st imulus to wake up the system. 10.3.2. stop mode setting the stop mode select bit (pcon.1) causes the ci p-51 to enter stop mode as soon as the instruc - tion that sets the bit comp letes execution. in stop mo de the internal oscillator, cpu, and all digital peripher - als are stopped; the st ate of the external oscillator circuit is not affected. each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mo de. stop mode can only be terminated by an internal or external reset. on reset, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout period of 100 s.
c8051f350/1/2/3 rev. 1.0 97 sfr definition 10.7. pcon: power control bits7?3: reserved. bit1: stop: stop mode select. writing a ?1? to this bit will place the cip-51 into stop mode. this bit will always read ?0?. 1: cip-51 forced into po wer-down mode. (turns of f internal oscillator). bit0: idle: idle mode select. writing a ?1? to this bit will place the cip-51 into idle mode. this bit will always read ?0?. 1: cip-51 forced into idle mode. (shuts off cl ock to cpu, but clock to timers, interrupts, and all peripherals remain active.) r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x87
c8051f350/1/2/3 98 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 99 11. memory organization and sfrs the memory organization of the c8051f350/1/2/3 is si milar to that of a standard 8051. there are two sep - arate memory spaces: program memory and data me mory. program and data memory share the same address space but are accessed via different in struction types. the memory map is shown in figure 11.1 . program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 512 bytes (accessable using movx instruction) 0x0000 0x01ff same 512 bytes as from 0x0000 to 0x01ff, wrapped on 512-byte boundaries 0x0200 0xffff 8k flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x1e00 0x1dff 0x1fff figure 11.1. memory map 11.1. program memory the cip-51 core has a 64 kb program memory space. th e c8051f350/1/2/3 implements 8 kb of this pro - gram memory space as in-system, re-programmable flash memory, organized in a contiguous block from addresses 0x0000 to 0x1dff. addresses above 0x1dff are reserved. program memory is normally assumed to be read-only. however, the c8051f350/1/2/3 can write to pro - gram memory by setting the program store write enable bit (psctl.0) and using the movx write instruc - tion. this feature provides a mec hanism for updates to program code and use of the program memory space for non-volatile data storage. refer to section ?15. flash memory? on page 121 for further details.
c8051f350/1/2/3 100 rev. 1.0 11.2. data memory the c8051f350/1/2/3 includes 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are a ddressable as four banks of general purpose registers, each bank con - sisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function registers (sfrs) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct address - ing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 11.1 illustrates the data memory organization of the c8051f350/1/2/3. the c8051f35x family also includes 512 bytes of on -chip ram mapped into the external memory (xdata) space. this ram can be accessed using the cip-51 core?s movx instruction. more information on the xram memory can be found in section ?16. external ram? on page 127 . 11.3. general purpose registers the lower 32 bytes of data memory (locations 0x00 through 0x1f) may be addressed as four banks of general-purpose registers. each bank consists of eight byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. tw o bits in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in sfr definition 10.4 ). this allows fast context switching when entering subrouti nes and interrupt service ro utines. indirect addressing modes use registers r0 and r1 as index registers. 11.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina - tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 11.5. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig - nated using the stack pointer (sp, 0x81) sfr. the sp will poin t to the last location used. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07. therefore, the first value pushed on the st ack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes.
c8051f350/1/2/3 rev. 1.0 101 11.6. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 805 1 implementation as well as implementing additional sfrs used to configure and access the sub-systems uni que to the mcu. this allows the addition of new functionality while retain ing compatibility with the mcs-51? instruction set. table 11.1 lists the sfrs implemented in the cip-51 system controller. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x 0 or 0x8 (e.g. p0, tcon, ie, etc.) are bit-addressable as well as byte-addressable. all other sfrs are byte -addressable only. unoccupied addresses in the sfr space are reserved for futu re use. accessing these areas will have an indetermin ate effect an d should be avoided. refer to the corresponding pages of the datasheet, as indicated in table 11.2 , for a detailed description of each register. table 11.1. special function register (sfr) memory map f8 spi0cn pca0l pca0h adc0cf adc0fl adc0fm adc0fh vdm0cn f0 b p0mdin p1mdin adc0md adc0cn eip1 adc0clk e8 adc0sta pca0cpl0 pca0cph0 pca0cpl1 p ca0cph1 pca0cpl2 pca0cph2 rstsrc e0 acc xbr0 xbr1 pfe0cn it01cf eie1 d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 ida1 d0 psw ref0cn p0skip p1skip ida1cn c8 tmr2cn tmr2rll tmr2rlh tmr2l tmr2h c0 smb0cn smb0cf smb0dat adc0l adc0m adc0h adc0mux b8 ip ida0cn adc0col adc0com adc0 coh adc0buf ckmul adc0dac b0 oscxcn oscicn oscicl flscl flkey a8 ie clksel emi0cn adc0cgl adc0cgm adc0cgh a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout 98 scon0 sbuf0 adc0decl adc0dec h cpt0cn cpt0md cpt0mx 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h ida0 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable)
c8051f350/1/2/3 102 rev. 1.0 table 11.2. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page acc 0xe0 accumulator 95 adc0buf 0xbd adc0 buffer control 53 adc0cf 0xfb adc0 configuration 49 adc0cgh 0xad adc0 gain calibration high 56 adc0cgl 0xab adc0 gain calibration low 56 adc0cgm 0xac adc0 gain calibration middle 56 adc0clk 0xf7 adc0 clock 51 adc0cn 0xf4 adc0 control 48 adc0coh 0xbc adc0 offset calibration high 55 adc0col 0xba adc0 offset calibration low 55 adc0com 0xbb adc0 offset calibration middle 55 adc0dac 0xbf adc0 offset dac 52 adc0dech 0x9b adc0 decimation high 51 adc0decl 0x9a adc0 decimation low 52 adc0fh 0xfe adc0 fast filter output high 58 adc0fl 0xfc adc0 fast filter output low 58 adc0fm 0xfd adc0 fast filter output middle 58 adc0h 0xc5 adc0 output high 57 adc0l 0xc3 adc0 output low 57 adc0m 0xc4 adc0 output middle 57 adc0md 0xf3 adc0 mode 50 adc0mux 0xc6 adc0 multiplexer 60 adc0sta 0xe8 adc0 status 54 b0xf0 b register 95 ckcon 0x8e clock control 201 clkmul 0xbe clock multiplier 135 clksel 0xa9 clock select 136 cpt0cn 0x9c comparator0 control 81 cpt0md 0x9d comparator0 mode selection 82 cpt0mx 0x9f comparator0 mux selection 84 dph 0x83 data pointer high 93 dpl 0x82 data pointer low 93 eie1 0xe6 extended interrupt enable 1 109 eip1 0xf6 extended interrupt priority 1 110 emi0cn 0xaa external memory interface control 127 flkey 0xb7 flash lock and key 125 flscl 0xb6 flash scale 126 ida0 0x96 current mode dac0 low 69 ida0cn 0xb9 current mode dac0 control 69 ida1 0xdd current mode dac1 low 70 ida1cn 0xd7 current mode dac1 control 70 ie 0xa8 interrupt enable 107 ip 0xb8 interrupt priority 108 it01cf 0xe4 int0/int1 configuration 112
c8051f350/1/2/3 rev. 1.0 103 oscicl 0xb3 internal oscillator calibration 130 oscicn 0xb2 internal oscillator control 130 oscxcn 0xb1 external oscillator control 134 p0 0x80 port 0 latch 145 p0mdin 0xf1 port 0 input mode configuration 145 p0mdout 0xa4 port 0 output mode configuration 146 p0skip 0xd4 port 0 skip 146 p1 0x90 port 1 latch 147 p1mdin 0xf2 port 1 input mode configuration 147 p1mdout 0xa5 port 1 output mode configuration 148 p1skip 0xd5 port 1 skip 148 p2 0xa0 port 2 latch 149 p2mdout 0xa6 port 2 output mode configuration 149 pca0cn 0xd8 pca control 222 pca0cph0 0xea pca capture 0 high 226 pca0cph1 0xec pca capture 1 high 226 pca0cph2 0xee pca capture 2 high 226 pca0cpl0 0xe9 pca capture 0 low 226 pca0cpl1 0xeb pca capture 1 low 226 pca0cpl2 0xed pca capture 2 low 226 pca0cpm0 0xda pca module 0 mode 224 pca0cpm1 0xdb pca module 1 mode 224 pca0cpm2 0xdc pca module 2 mode 224 pca0h 0xfa pca counter high 225 pca0l 0xf9 pca counter low 225 pca0md 0xd9 pca mode 223 pcon 0x87 power control 97 pfe0cn 0xe3 prefetch engine control 113 psctl 0x8f program store r/w control 125 psw 0xd0 program status word 94 ref0cn 0xd1 voltage reference control 74 rstsrc 0xef reset source configuration/status 119 sbuf0 0x99 uart0 data buffer 177 scon0 0x98 uart0 control 176 smb0cf 0xc1 smbus configuration 158 smb0cn 0xc0 smbus control 160 smb0dat 0xc2 smbus data 162 sp 0x81 stack pointer 93 spi0cfg 0xa1 spi configuration 187 spi0ckr 0xa2 spi clock rate control 189 spi0cn 0xf8 spi control 188 spi0dat 0xa3 spi data 190 tcon 0x88 timer/counter control 199 th0 0x8c timer/counter 0 high 202 th1 0x8d timer/counter 1 high 202 table 11.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
c8051f350/1/2/3 104 rev. 1.0 tl0 0x8a timer/counter 0 low 202 tl1 0x8b timer/counter 1 low 202 tmod 0x89 timer/counter mode 200 tmr2cn 0xc8 timer/counter 2 control 205 tmr2h 0xcd timer/counter 2 high 206 tmr2l 0xcc timer/counter 2 low 206 tmr2rlh 0xcb timer/counter 2 reload high 206 tmr2rll 0xca timer/counter 2 reload low 206 tmr3cn 0x91 timer/counter 3control 209 tmr3h 0x95 timer/counter 3 high 210 tmr3l 0x94 timer/counter 3 low 210 tmr3rlh 0x93 timer/counter 3 reload high 210 tmr3rll 0x92 timer/counter 3 reload low 210 vdm0cn 0xff v dd monitor control 117 xbr0 0xe1 port i/o crossbar control 0 142 xbr1 0xe2 port i/o crossbar control 1 143 table 11.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
c8051f350/1/2/3 rev. 1.0 105 12. interrupt handler the c8051f35x family includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. the allocati on of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. each interrupt source has one or more associ - ated interrupt-pending flag(s) located in an sfr. when a peripheral or external source meets a valid inter - rupt condition, the associated interr upt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede - termined address to begin execution of an interrupt se rvice routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal . (the interrupt-pending flag is set to logic 1 regard - less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the interrupt enable and extended interrupt enable sfrs. however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are recog - nized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt- enable settings. note that interrupts which occur wh en the ea bit is set to logic 0 will be held in a pending state, and will not be serviced until the ea bit is set back to logic 1. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of th e next instruction. 12.1. mcu interrupt sources and vectors the mcus support 12 interrupt sources. software can simulate an interrupt by setting any interrupt-pend - ing flag to logic 1. if interrupts are enab led for the flag, an in terrupt reque st will be generat ed and the cpu will vector to the isr address associ ated with the interrup t-pending flag. mcu inte rrupt sources, associ - ated vector addresses, priority order and control bits are summarized in ta b l e 12.1 on page 106 . refer to the datasheet section associated with a particular on-c hip peripheral for information regarding valid inter - rupt conditions for the peri pheral and the behavior of its interrupt-pending flag(s). 12.2. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior - ity interrupt service routine can be pree mpted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip1) used to configure its priority level. low priority is th e default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in ta b l e 12.1 . 12.3. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall
c8051f350/1/2/3 106 rev. 1.0 is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new in terrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycles to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. table 12.1. interrupt summary reset 0x0000 to p none n/a n/a always enabled always highest external interrupt 0
c8051f350/1/2/3 rev. 1.0 107 12.4. interrupt register descriptions the sfrs used to enable the interrupt sources and set t heir priority level are described below. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). sfr definition 12.1. ie: interrupt enable bit 7: ea: enable all interrupts. this bit globally enables/disabl es all interrupts. it overrides the individual interrupt mask set- tings. 0: disable all interrupt sources. 1: enable each interrupt accord ing to its individual mask setting. bit 6: espi0: enable seri al peripheral interf ace (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. bit 5: et2: enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. bit 4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable ua rt0 interrupt. bit 3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all ti mer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. bit 2: ex1: enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 input. bit 1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all ti mer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. bit 0: ex0: enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 input. r/w r/w r/w r/w r/w r/w r/w r/w reset value ea espi0 et2 es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xa8
c8051f350/1/2/3 108 rev. 1.0 sfr definition 12.2. ip: interrupt priority bit 7: unused. read = 1, write = don't care. bit 6: pspi0: serial periph eral interface (spi0) in terrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. bit 5: pt2: timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. bit 4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. bit 3: pt1: timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. bit 2: px1: external interr upt 1 priority control. this bit sets the priority of the ex ternal interrupt 1 interrupt. 0: external interrupt 1 set to low priority level. 1: external interrupt 1 set to high priority level. bit 1: pt0: timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. bit 0: px0: external interr upt 0 priority control. this bit sets the priority of the ex ternal interrupt 0 interrupt. 0: external interrupt 0 set to low priority level. 1: external interrupt 0 set to high priority level. r r/w r/w r/w r/w r/w r/w r/w reset value ? pspi0 pt2 ps0 pt1 px1 pt0 px0 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xb8
c8051f350/1/2/3 rev. 1.0 109 sfr definition 12.3. eie1: extended interrupt enable 1 bit 7: et3: enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. bit 6: reserved. read = 0. must write 0. bit 5: ecp0: enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. bit 4: epca0: enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. bit 3: eadc0: enable adc0 co nversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conver sion complete interrupt. 1: enable interrupt requests generated by the ad0int flag. bits 2?1: reserved. read = 00. must write 00. bit 0: esmb0: enable smbu s (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0. r/w r/w r/w r/w r/w r/w r/w r/w reset value et3 reserved ecp0 epca0 eadc0 re served reserved esmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe6
c8051f350/1/2/3 110 rev. 1.0 sfr definition 12.4. eip1: extended interrupt priority 1 bit 7: pt3: timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts se t to low priority level. 1: timer 3 interrupts set to high priority level. bit 6: reserved. read = 0. must write 0. bit 5: pcp0: comparator0 (cp0) interrupt prio rity control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. bit 4: ppca0: programmable counter arra y (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. bit 3: padc0 adc0 conversion comp lete interrupt pr iority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete inte rrupt set to high priority level. bits 2?1: reserved. read = 00. must write 00. bit 0: psmb0: smbus (smb0) in terrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value pt3 reserved pcp0 ppca0 padc0 reserved reserved psmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf6
c8051f350/1/2/3 rev. 1.0 111 12.5. external interrupts the /int0 and /int1 external interrupt sources are confi gurable as active high or low, edge or level sensi - tive. the in0pl (/int0 polarity) and in1pl (/int1 polarity ) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon ( section ?22.1. timer 0 and timer 1? on page 195 ) select level or edge sensitive. the table below lists the possible configurations. active low, edge sensitive active low, edge sensitive active high, edge sensitive active high, edge sensitive active low, level sensitive active low, level sensitive active high, level sensitive active high, level sensitive /int0 and /int1 are assigned to port pins as defined in the it01cf register (see sfr definition 12.5). note that /int0 and /int0 port pin assignments are independent of any crossbar assignments. /int0 and /int1 will monitor their assigned port pins without disturbing th e peripheral that was assigned the port pin via the crossbar. to assign a port pin only to /int 0 and/or /int1, configure the crossbar to skip the selected pin(s). this is accomplished by setti ng the associated bit in register xbr0 (see section ?18.1. priority crossbar decoder? on page 139 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interr upt-pending flags for the /int0 and /int1 external interrupts, respectively. if an /int0 or /int1 external interrupt is configured as edge-sensitive, the corre - sponding interrupt-pending flag is automatically clear ed by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pendi ng flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in 1pl); the flag remains logi c 0 while the input is inac - tive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrup t request before execution of the isr completes or another interrupt request will be generated. it0 in0pl /int0 interrupt it1 in1pl /int1 interrupt 10 10 11 11 00 00 01 01
c8051f350/1/2/3 112 rev. 1.0 sfr definition 12.5. it01cf: int0/int 1 configuration bit 7: in1pl: /int1 polarity 0: /int1 input is active low. 1: /int1 input is active high. bits 6?4: in1sl2?0: /int1 port pin selection bits these bits select which port pin is assigned to /int1. note that this pin assignment is inde- pendent of the crossbar; /int 1 will monitor the assigned port pin without disturbing the peripheral that has been assi gned the port pin via the cr ossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). bit 3: in0pl: /int0 polarity 0: /int0 interrupt is active low. 1: /int0 interrupt is active high. bits 2?0: int0sl2?0: /int0 port pin selection bits these bits select which port pin is assigned to /int0. note that this pin assignment is inde- pendent of the crossbar. /int 0 will monitor the assigned port pin without disturbing the peripheral that has been assi gned the port pin via the cr ossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). r/w r/w r/w r/w r/w r/w r/w r/w reset value in1pl in1sl2 in1sl1 in1sl0 in0pl in0sl2 in0sl1 in0sl0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe4 note: refer to sfr definition 22.1 for int0/1 edge- or level-sensitive interrupt selection. in1sl2?0 /int1 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 in0sl2?0 /int0 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7
c8051f350/1/2/3 rev. 1.0 113 13. prefetch engine the c8051f350/1/2/3 family of devices incorporate a 2-byte prefetch engine. because the access time of the flash memory is 40 ns, and the minimum instruction time is 20 ns, the prefetch engine is necessary for full-speed code execution. instructions are read from flash memory two bytes at a time by the prefetch engine, and given to the cip-51 processor core to execute. when running linear code (code without any jumps or branches), the prefetch engine allows instru ctions to be executed at full speed. when a code branch occurs, the processor may be stalled for up to tw o clock cycles while the next set of code bytes is retrieved from flash memory. the fl rt bit (flscl.4) determines how ma ny clock cycles are used to read each set of two code bytes from flash. when operating from a system clock of 25 mhz or less, the flrt bit should be set to ?0? so that the prefetch engine takes only one clock cycle for each read. when operat - ing with a system clock of greater than 25 mhz (up to 50 mhz), the flrt bit should be set to ?1?, so that each prefetch code read lasts for two clock cycles. sfr definition 13.1. pfe0cn: prefetch engine control bits 7?6: unused. read = 00b; write = don?t care bit 5: pfen: prefetch enable. this bit enables the prefetch engine. 0: prefetch engine is disabled. 1: prefetch engine is enabled. bits 4?1: unused. read = 0000b; write = don?t care bit 0: flbwe: flash block write enable. this bit allows block writes to flash memory from software. 0: each byte of a software fl ash write is written individually. 1: flash bytes are written in groups of two. r r r/w r r r r r/w reset value pfen flbwe 00100000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe3
c8051f350/1/2/3 114 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 115 14. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones ) in open-drain mode. weak pull-ups are enabled dur - ing and after the reset. for v dd monitor and power-on resets, the /rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter - nal oscillator. refer to section ?17. oscillators? on page 129 for information on selecting and configuring the system clock source. the watchdog timer is enabled with the system clock divided by 12 as its clock source ( section ?23.3. watchdog timer mode? on page 220 details the use of the watchdog timer). program execution begins at location 0x0000. pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable errant flash operation /rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable figure 14.1. reset sources
c8051f350/1/2/3 116 rev. 1.0 14.1. power-on reset during power-up, the device is held in a rese t state and the /rst pin is driven low until v dd settles above v rst . an additional delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 14.2 . plots the power-on and v dd monitor reset timing. for valid ramp times (less than 1 ms), the power-on reset delay (t pordelay ) is typically less than 0.3 ms. note: the maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from reset before v dd reaches the v rst level. on exit from a power-on reset, the porsf fl ag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was the cause of reset. the contents of internal data memory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. power-on reset vdd monitor reset /rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.55 v rst vdd figure 14.2. power-on and v dd monitor reset timing
c8051f350/1/2/3 rev. 1.0 117 14.2. power-fail reset / v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the /rst pin low and ho ld the cip-51 in a reset state (see figure 14.2 ). when v dd returns to a level above v rst , the cip-51 will be released from the re set state. note that even though inter - nal data memory contents are not altered by the powe r-fail reset, it is imposs ible to determine if v dd dropped below the level required for data retention. if the porsf flag reads ?1?, the data may no longer be valid. the v dd monitor is enabled and selected as a reset source after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled by software, and a software reset is performed, the v dd monitor will still be disabled after the reset. to protect the integrity of flash contents, it is strongly recommended that the v dd monitor remain enabled and selected as a reset source if software contains routines which erase or write flash memory. the v dd monitor must be enabled before it is se lected as a reset source. selecting the v dd monitor as a reset source before it is enabled and stabilized may cause a system reset. the procedure for re-enabling the v dd monitor and configuring the v dd monitor as a reset so urce is shown below: step 1. enable the v dd monitor (vdmen bit in vdm0cn = ?1?). step 2. wait for the v dd monitor to stabilize (see table 14.1 for the v dd monitor turn-on time). note: this delay should be omitted if software contains routines which erase or write flash memory. step 3. select the v dd monitor as a reset source (porsf bit in rstsrc = ?1?). see figure 14.2 for v dd monitor timing; note that the reset delay is not incurred after a v dd monitor reset. see ta b l e 14.1 for complete electrical characteristics of the v dd monitor. sfr definition 14.1. vdm0cn: v dd monitor control bit7: vdmen: v dd monitor enable. this bit is turns the v dd monitor circuit on/off. the v dd monitor cannot generate system resets until it is also selected as a reset source in register rstsrc (sfr definition 14.2). the v dd monitor must be allowed to stabilize befo re it is selected as a reset source. select- ing the v dd monitor as a reset source before it has stabilized may generate a system reset. see table 14.1 for the minimum v dd monitor turn-on time. 0: v dd monitor disabled. 1: v dd monitor enabled (default). bit6: v dd stat: v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. bits5?0: reserved. read = variable. write = don?t care. r/w r r r r r r r reset value vdmen v dd stat reserved reserved reserved reserved reserved reserved variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xff
c8051f350/1/2/3 118 rev. 1.0 14.3. external reset the external /rst pin provides a means for external ci rcuitry to force the device into a reset state. assert - ing an active-low signal on the /rst pin generates a reset; an external pull-up and/or decoupling of the /rst pin may be necessary to avoid erroneous noise-induced resets. see ta b l e 14.1 for complete /rst pin specifications. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 14.4. missing clock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the syst em clock. if the system clock remains high or low for more than 100 s, the one-shot will time out an d generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read ?1?, signifying the mcd as the reset source; otherwise, this bit reads ?0?. writing a ?1? to the mcdrsf bit enables the missing clo ck detector; writing a ?0? disables it. the state of the /rst pin is unaffected by this reset. 14.5. comparator0 reset comparator0 can be configured as a reset source by writing a ?1? to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0?), the device is put into the reset state. afte r a comparator0 reset, the c0rsef flag (rstsrc.5) will read ?1? signifying comparator0 as the reset source; otherwise, this bit reads ?0?. the state of the /rst pin is unaffected by this reset. 14.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as described in section ?23.3. watchdog timer mode? on page 220 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is generated and the wdtrsf bit (rstsrc.5) is set to ?1?. the state of the /rst pin is unaffected by this reset. 14.7. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to ?1? and a movx write operation targets an address above address 0x1dff. ? a flash read is attempted above user code space. this occurs when a movc operation targets an address above address 0x1dff. ? a program read is attempted above user code spac e. this occurs when user code attempts to branch to an address above 0x1dff. ? a flash read, write or erase attempt is re stricted due to a flash security setting (see section ?15.3. security options? on page 123 ). the ferror bit (rstsrc.6) is set following a flash erro r reset. the state of the /rst pin is unaffected by this reset. 14.8. software reset software may force a reset by writ ing a ?1? to the swrsf bit (rstsrc.4). the swrsf bit will read ?1? fol - lowing a software forced reset. the state of the /rst pin is unaffected by this reset.
c8051f350/1/2/3 rev. 1.0 119 sfr definition 14.2. rstsrc: reset source bit7: unused. read = 0. write = don?t care. bit6: ferror: flash error indicator. 0: source of last reset was not a flash read/write/erase error. 1: source of last reset was a flash read/write/erase error. bit5: c0rsef: comparator0 reset enable and flag. 0: read: source of last reset was not comparator0. write: comparator0 is not a reset source. 1: read: source of last reset was comparator0. write: comparator0 is a reset source (active-low). bit4: swrsf: software reset force and flag. 0: read: source of last reset was no t a write to the swrsf bit. write: no effect. 1: read: source of last was a write to the swrsf bit. write: forces a system reset. bit3: wdtrsf: watchdog timer reset flag. 0: source of last reset was not a wdt timeout. 1: source of last reset was a wdt timeout. bit2: mcdrsf: missing clock detector flag. 0: read: source of last reset was not a missing clock detector timeout. write: missing clock detector disabled. 1: read: source of last reset was a mi ssing clock detector timeout. write: missing clock detector enabled; triggers a reset if a missing clock condition is detected. bit1: porsf: power-on reset force and flag. this bit is set anytime a power-on reset occurs. writing this bit enables/disables the v dd monitor as a reset source. note: writing ?1? to this bit before the v dd monitor is enabled and stabilized may cause a system reset. see register vdm0cn (sfr definition 14.1) 0: read: last reset was not a power-on or v dd monitor reset. write: v dd monitor is not a reset source. 1: read: last reset was a power-on or v dd monitor reset; all other reset flags indeterminate. write: v dd monitor is a reset source. bit0: pinrsf: hw pin reset flag. 0: source of last re set was not /rst pin. 1: source of last reset was /rst pin. r r r/w r/w r r/w r/w r reset value ? ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xef
table 14.1. reset electrical characteristics c8051f350/1/2/3 120 rev. 1.0 ?40 to +85 c unless otherwise specified. parameter conditions min typ max units /rst output low voltage i ol = 8.5 ma, v dd = 2.7 to 3.6 v 0.6 v /rst input high voltage 0.7 x v dd v /rst input low voltage 0.3 x v dd /rst input pullup current /rst = 0.0 v 25 40 a v dd monitor threshold (v rst ) 2.40 2.55 2.70 v missing clock detector timeout time from last system clock rising edge to reset initiation 100 220 600 s reset time delay delay between release of any reset source and code execution at loca- tion 0x0000 5.0 s minimum /rst low time to generate a system reset 15 s v dd monitor turn-on time 100 s v dd monitor supply current 20 50 a v dd ramp time v dd = 0 v to v rst ??1ms
c8051f350/1/2/3 rev. 1.0 121 15. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system through the c2 interface or by software using the movx instruction. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automat - ically timed by hardware for proper execution; data polling to dete rmine the end of th e write/erase opera - tion is not required. code execution is stalle d during a flash write/erase operation. refer to table 15.1 for complete flash memory el ectrical characteristics. 15.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial - ized device. for details on the c2 commands to program flash memory, see section ?24. c2 interface? on page 227 . to ensure the integrity of flash contents, it is strongly recommended that the on-chip v dd monitor be enabled in any system that includes code that writes and/or erases flash memory from soft - ware. 15.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. th e flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per - formed. the flkey regist er is detailed in sfr definition 15.2 . 15.1.2. flash erase procedure the flash memory can be programmed by software using the movx write instru ction with the address and data byte to be programmed provided as normal ope rands. before writing to flash memory using movx, flash write operations must be enabled by: (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target fl ash memory); and (2) writing the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set until cleared by soft - ware. a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. the flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: step 1. disable interrupts (recommended). step 2. set thepsee bit (register psctl). step 3. set the pswe bit (register psctl). step 4. write the first key code to flkey: 0xa5. step 5. write the second key code to flkey: 0xf1. step 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. step 7. clear the pswe and psee bits. step 8. re-enable interrupts.
c8051f350/1/2/3 122 rev. 1.0 15.1.3. flash write procedure bytes in flash memory can be written one byte at a time, or in groups of two. the flbwe bit in register pfe0cn ( sfr definition 13.1 ) controls whether a single byte or a block of two bytes is written to flash during a write operation. when flbwe is cleared to ?0?, the flash will be written one byte at a time. when flbwe is set to ?1?, the flash will be written in two-byte blocks. block writes are performed in the same amount of time as single-byte writes, which can save time when storing large amounts of data to flash memory. during a single-byte write to flas h, bytes are written individually, a nd a flash write will be performed after each movx write instruction. the recommended pr ocedure for writing flash in single bytes is: step 1. disable interrupts. step 2. clear the flbwe bit (register pfe0cn) to select single-byte write mode. step 3. set the pswe bit (register psctl). step 4. clear the psee bit (register psctl). step 5. write the first key code to flkey: 0xa5. step 6. write the second key code to flkey: 0xf1. step 7. using the movx instruction, write a single data byte to the desired location within the 512- byte sector. step 8. clear the pswe bit. step 9. re-enable interrupts. steps 5?7 must be repeated for each byte to be written. for block flash writes, the flash write procedure is only performed after the last byte of each block is writ - ten with the movx write instru ction. a flash write block is two by tes long, from even addresses to odd addresses. writes must be performed sequentially (i.e . addresses ending in 0b and 1b must be written in order). the flash write will be perform ed following the movx write that target s the address ending in 1b. if a byte in the block does not need to be updated in fl ash, it should be written to 0xff. the recommended procedure for writing flash in blocks is: step 1. disable interrupts. step 2. set the flbwe bit (resgister pfe0cn) to select block write mode. step 3. set the pswe bit (register psctl). step 4. clear the psee bit (register psctl). step 5. write the first key code to flkey: 0xa5. step 6. write the second key code to flkey: 0xf1. step 7. using the movx instruction, write the first data byte to the even block location (ending in 0b). step 8. write the first key code to flkey: 0xa5. step 9. write the second key code to flkey: 0xf1. step 10. using the movx instruction, write the second data byte to the odd block location (ending in 1b). step 11. clear the pswe bit. step 12. re-enable interrupts. steps 5?10 must be repeated for each block to be written.
c8051f350/1/2/3 rev. 1.0 123 15.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instructi on. note: movx read instructions always target xram. 15.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft - ware as well as to prevent the viewing of proprietary program code and constants. the program store write enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash me mory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, or erases) by unpr otected code or the c2 inte rface. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x01ff), where n is the 1?s complement number represented by the security lock byte. note that the page containing the flash security lock byte is lo cked when any other flash pages are locked. see exam - ple below. access limit set according to the flash security lock byte 0x0000 0x1dff lock byte reserved 0x1dfe 0x1e00 flash memory organized in 512-byte pages 0x1c00 unlocked flash pages locked when any other flash pages are locked figure 15.1. flash memory map security lock byte: 11111101b 1?s complement: 00000010b flash pages locked: 3 (first two flash pages + lock byte page) addresses locked: 0x0000 to 0x03ff (first two flash pages) and 0x1c00 to 0x1dff (lock byte page)
c8051f350/1/2/3 124 rev. 1.0 the level of flash security depends on the flash ac cess method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. accessing flash from the c2 debug interface: 1. any unlocked page may be read, written, or erased. 2. locked pages cannot be read, written, or erased. 3. the page containing the lock byte may be read , written, or erased if it is unlocked. 4. reading the contents of the lock byte is always permitted only if no pages are locked. 5. locking additional pages (changing ?1?s to ?0?s in the lock byte) is not permitted. 6. unlocking flash pages (changing ?0?s to ?1?s in the lock byte) requires the c2 device erase command, which erases all flash pages including the page containing the lock byte and the lock byte itself. 7. the reserved area cannot be read, written, or erased. accessing flash from user firmware executing from an unlocked page: 1. any unlocked page except the page containing the lock byte may be read, written, or erased. 2. locked pages cannot be read, written, or erased. an erase attempt on the page containing the lock byte will result in a flash error device reset. 3. the page containing the lock byte cannot be erased. it may be read or written only if it is unlocked. an erase attempt on the page contai ning the lock byte will re sult in a flash error device reset. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing ?1?s to ?0?s in the lock byte) is not permitted. 6. unlocking flash pages (changing ?0?s to ?1?s in the lock byte) is not permitted. 7. the reserved area cannot be read, written, or erased. any attempt to access the reserved area, or any other locked page, will re sult in a flash error device reset. accessing flash from user firmware executing from a locked page: 1. any unlocked page except the page containing t he lock byte may be read, written, or erased. 2. any locked page except the page containing the lock byte may be read, written, or erased. an erase attempt on the page cont aining the lock byte will result in a flash error device reset. 3. the page containing the lock byte cannot be erased. it may only be read or written. an erase attempt on the page containing the lock byte will result in a flash error device reset. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing ?1?s to ?0?s in the lock byte) is not permitted. 6. unlocking flash pages (changing ?0?s to ?1?s in the lock byte) is not permitted. 7. the reserved area cannot be read, written, or erased. any attempt to access the reserved area, or any other locked page, will re sult in a flash error device reset.
c8051f350/1/2/3 rev. 1.0 125 sfr definition 15.1. psctl: program store r/w control bits7?2: unused: read = 000000b, write = don?t care. bit1: psee: program store erase enable setting this bit (in combination with pswe) a llows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx in struction will erase the entire page that contains the loca- tion addressed by the movx instruction. the va lue of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. bit0: pswe: program store write enable setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx write instruction targets flash memory. rrrrrrr/wr/wreset value ? ? ? ? ? ? psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8f sfr definition 15.2. flkey: flash lock and key bits7?0: flkey: flash lock and key register write: this register provides a lock and key function for flash erasures and writes. flash writes and erases are enabled by writing 0xa5 fo llowed by 0xf1 to th e flkey register. flash writes and erases are aut omatically disabled after the next write or erase is complete. if any writes to flkey are performed inco rrectly, or if a fl ash write or erase ope ration is attempted while these operations are dis abled, the flash will be permanently locked fr om writes or era- sures until the next device reset. if an applicat ion never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (w rites/erases allowed). 11: flash writes/erases disa bled until the next reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb7
c8051f350/1/2/3 126 rev. 1.0 sfr definition 15.3. flscl: flash scale bits7?5: reserved. read = 000b. must write 000b. bit 4: flrt: flash read time. this bit should be programmed to the smallest allowed value, according to the system clock speed. 0: sysclk < 25 mhz. 1: sysclk < 50 mhz. bits3?0: reserved. read = 0000b. must write 0000b. r/w r/w r/w r/w r/w r/w r/w r/w reset value reserved reserved reserved flrt reserved reserved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb6 table 15.1. flash electrical characteristics *note: 512 bytes at addresses 0x1e00 to 0x1fff are reserved. v dd = 2.7 to 3.6 v; ?40 to +85 oc unless otherwise specified parameter conditions min typ max units flash size c8051f350/1/2/3 8192* bytes endurance 20 k 100 k erase/write erase cycle time 50 mhz system clock 10 15 20 ms write cycle time 50 mhz system clock 40 55 70 s
c8051f350/1/2/3 rev. 1.0 127 16. external ram the c8051f350/1/2/3 devices include 512 bytes of ram mapped into the external data memory space. all of these address locations may be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode. if the movx instruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit address is provided by the external mem - ory interface control register (emi0cn as shown in sfr definition 16.1 ). note: the movx instruction is also used for writes to the flash memory. see section ?15. flash memory? on page 121 for details. the movx instruction accesses xram by default. for a 16-bit movx operation (@dptr), the upper 6-bits of the 16-bit external data memory address word are "don't cares". as a result, the 512-byte ram is mapped modulo style over the entire 64 k external data memory address range. for example, the xram byte at address 0x0000 is shadowed at addresses 0x0200, 0x0400, 0x0600, 0x0800, etc. this is a useful feature when perf orming a linear memory fill, as the address pointer doesn't have to be reset when reaching the ram block boundary. sfr definition 16.1. emi0cn: external memo ry interface control bits 7?1: unused. read = 0000000b. write = don?t care. bit 0: pgsel: xram page select. the emi0cn register provides the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectivel y selecting a 256-byte page of ram. since the upper (unused) bits of the register are always zero, the pgsel determines which page of xram is accessed. for example: if emi0cn = 0x01, addresse s 0x0100 through 0x01ff will be accessed. r/w r/w r/w r/w r/w r/w r/w r/w reset value ???????pgsel00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xaa
c8051f350/1/2/3 128 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 129 17. oscillators c8051f350/1/2/3 devices incl ude a programma ble internal oscillator, an exte rnal oscillator drive circuit, and a clock multiplier. the internal oscillator can be enab led/disabled and calib rated using the oscicn and oscicl registers, as shown in figure 17.1 . the system clock (sysclk) can be derived from the internal oscillator, external oscillator circuit, or the clock multiplier. the clock multiplier can produce three possible outputs: internal oscillator x 2, external oscillator x 2, or external oscillator x 4. oscillator electri - cal specifications are given in ta b l e 17.1 on page 136 . clock multiplier osc exosc input circuit xtlvld xtal1 xtal2 option 2 vdd xtal2 option 1 10m ?
c8051f350/1/2/3 130 rev. 1.0 sfr definition 17.1. oscicn: internal os cillator control bit7: ioscen: internal oscillator enable bit. 0: internal osc illator disabled. 1: internal oscillator enabled. bit6: ifrdy: internal oscilla tor frequency ready flag. 0: internal oscillator is not running at prog rammed frequency. 1: internal oscillator is r unning at progra mmed frequency. bits5?2: unused. read = 0000b, write = don't care. bits1?0: ifcn1?0: internal osc illator frequency control bits. 00: sysclk derived from intern al oscillator divided by 8. 01: sysclk derived from intern al oscillator divided by 4. 10: sysclk derived from intern al oscillator divided by 2. 11: sysclk derived from internal oscillator divided by 1. r/w r r r r r r/w r/w reset value ioscen ifrdy ? ? ? ? ifcn1 ifcn0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb2 sfr definition 17.2. oscicl: internal osci llator calibration bit7: unused. read = 0. write = don?t care. bits 6?0: oscicl: internal os cillator calibration register. this register determines the internal oscilla tor period. on c8051f35 0/1/2/3 devices, the reset value is factory calibrate d to generate an in ternal oscillator frequency of 24.5 mhz. r r/w r/w r/w r/w r/w r/w r/w reset value variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb3
c8051f350/1/2/3 rev. 1.0 131 17.2. external oscill ator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. for a cr ystal or ceramic resonator configuration, the crys - tal/resonator must be wired across the xtal 1 and xtal2 pins as shown in option 1 of figure 17.1 . a 10 m ? resistor also must be wired across the xtal1 an d xtal2 pins for the crystal/resonator configura - tion. in rc, capacitor, or cmos cl ock configuration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 17.1 . the type of external oscillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see sfr definition 17.3 ) important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal/r esonator mode, port pins p0.2 and p0.3 are used as xtal1 and xtal2 respectively. when the ex ternal oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is used as xtal2. the port i/o crossbar should be configured to ski p the port pins used by the oscillator circuit; see section ?18.1. priority cross - bar decoder? on page 139 for crossbar configuratio n. additionally, when using the external oscillator cir - cuit in crystal/resonator, capacitor, or rc mode, the as sociated port pins should be configured as analog inputs. in cmos clock mode, the associated pin should be configured as a digital input . see section ?18.2. port i/o initialization? on page 141 for details on port input mode selection. 17.2.1. clocking timers directly through the external oscillator the external oscillator source divided by eight is a clock option for the timers ( section ?22. timers? on page 195 ) and the programmable counter array (pca) ( section ?23. programmable counter array? on page 211 ). when the external os cillator is used to clock these peri pherals, but is not used as the sys - tem clock, the external osc illator frequency must be le ss than or equal to the system clock frequency. in this configuration, the clock supplie d to the peripheral (external oscillato r / 8) is synchronized with the sys - tem clock; the jitter asso ciated with this synchronization is limited to 0.5 system clock cycles. 17.2.2. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 17.1 , option 1. the external oscillato r frequency contro l value (xfcn) should be chosen from the crystal column of the table in sfr definition 17.3 (oscxcn register). for example, a 12 mhz crystal requires an xfcn setting of 111b. when the crystal oscillator is first e nabled, the oscillator amplitude detecti on circuit requires a settling time to achieve proper bias. introducing a delay of 1 ms between enabling the o scillator and checking the xtlvld bit will prevent a premature switch to the extern al oscillator as the system clock. switching to the external oscillator before the crysta l oscillator has stabilized can result in unpredictable behavior. the rec - ommended procedure is: step 1. force the xtal1 and xtal2 pins low by writing 0?s to the port latch. step 2. configure xtal1 and xtal2 as analog inputs. step 3. enable the external oscillator. step 4. wait at least 1 ms. step 5. poll for xtlvld => ?1?. step 6. switch the system cl ock to the external oscillator. note: tuning-fork crystals may require additional se ttling time before xtlvld returns a valid result.
c8051f350/1/2/3 132 rev. 1.0 the capacitors shown in the external crystal configur ation provide the load capacitance required by the crystal for correct oscillation. these capacitors are ?in series? as seen by the crystal and ?in parallel? with the stray capacitance of the xtal1 and xtal2 pins. note: the load capacitance depends upon the crystal and the manufacturer. please refer to the crystal datasheet when completing these calculations. for example, a tuning-fork crystal of 32.768 khz with a recommended load capacitance of 12.5 pf should use the configuration shown in figure 17.1 , option 1. the total value of the capacitors and the stray capacitance of the xtal pins should equal 25 pf. wi th a stray capacitance of 3 pf per pin, the 22 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 17.2 . 22 pf 22 pf 32.768 khz 10 m xtal1 xtal2 ?
c8051f350/1/2/3 rev. 1.0 133 17.2.3. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 17.1 , option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter - mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscilla tion. if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 * 50 ] = 0.1 mhz = 100 khz referring to the table in sfr defini tion 17.3, the required xfcn setting is 010b. programming xfcn to a higher setting in rc mode will improv e frequency accuracy at an increa sed external osc illator supply cur - rent. 17.2.4. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 17.1 , option 3. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasiti c capacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci - tor to be used and find the fr equency of oscillati on from the equations below. assume v dd = 3.0 v and f = 150 khz: f = kf / (c x v dd ) 0.150 mhz = kf / (c x 3.0) since the frequency of roughly 150 khz is desired, sele ct the k factor from the table in sfr definition 17.3 as kf = 22: 0.150 mhz = 22 / (c x 3.0) c x 3.0 = 22 / 0.150 mhz c = 146.6 / 3.0 pf = 48.8 pf therefore, the xfcn value to use in this example is 011b and c = 50 pf.
c8051f350/1/2/3 134 rev. 1.0 sfr definition 17.3. oscxcn: external oscillator control bit7: xtlvld: crystal oscillator valid flag. (read only when xoscmd = 11x.) 0: crystal oscillator is unused or not yet stable. 1: crystal oscillator is running and stable. bits6?4: xoscmd2?0: extern al oscillator mode bits. 00x: external osc illator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. bit3: reserved. read = 0, write = don't care. bits2?0: xfcn2?0: external osc illator frequency control bits. 000?111: see table below: crystal mode (circuit from figure 17.1 , option 1; xoscmd = 11x) choose xfcn value to match crystal or resonator frequency. rc mode (circuit from figure 17.1, option 2; xoscmd = 10x) choose xfcn value to match frequency range: f = 1.23(10 3 ) / (r * c) , where f = frequency of clock in mhz c = capacitor value in pf r = pull-up resist or value in k ? < < < < < < < < < < < < < <
c8051f350/1/2/3 rev. 1.0 135 17.3. clock multiplier the clock multiplier generate s an output clock which is 4 times the input clock frequency. the clock multi - plier?s input can be selected from the external oscillator, or 1/2 the inter nal or external os cillators. this pro - duces three possible outpu ts: internal oscillator x 2, external oscillator x 2, or external oscillator x 4. see section 17.4 for details on system clock selection. the clock multiplier is configured vi a the clkmul register (sfr definition 17.4). the procedure for con - figuring and enabling the cloc k multiplier is as follows: 1. reset the multiplier by writ ing 0x00 to register clkmul. 2. select the multiplier input source via the mulsel bits. 3. enable the multiplier with the mulen bit (clkmul | = 0x80). 4. delay for >5 s. 5. initialize the multip lier with the mulinit bit (clkmul | = 0xc0). 6. poll for mulrdy => ?1?. important note: when using an external oscillator as the input to the clock multiplier, the external source must be enabled and stable befo re the multiplier is initialized. see section 17.4 for details on selecting an external oscillator source. sfr definition 17.4. clkmul: clock multiplier control bit7: mulen: clock multiplier enable 0: clock multiplier disabled. 1: clock multiplier enabled. bit6: mulinit: clock multiplier initialize this bit should be a ?0? when the clock multiplie r is enabled. once enabled, writing a ?1? to this bit will initialize the clock multiplier. the mu lrdy bit reads ?1? when the clock multiplier is stabilized. bit5: mulrdy: clock multiplier ready this read-only bit indicates th e status of the clock multiplier. 0: clock multiplier not ready. 1: clock multiplier ready (locked). bits4?2: unused. read = 000b; write = don?t care. bits1?0: mulsel: clock mu ltiplier input select these bits select the clock supplied to the clock multiplier. r/w r/w r r/w r/w r/w r/w r/w reset value mulen mulinit mulrdy ? ? ? mulsel 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbe mulsel selected input clock clock multipler output 00 internal oscillator / 2 internal oscillator x 2 01 external oscillator e xternal oscillator x 4 10 external oscillator / 2 external oscillator x 2 11 reserved reserved
c8051f350/1/2/3 136 rev. 1.0 17.4. system clock selection the internal oscillator requir es little start-up time and may be selected as the s ystem clock immediately fol - lowing the oscicn write that enables the internal oscillator. external crystals and ceramic resonators typ - ically require a start-up time before they are settle d and ready for use. the crystal valid flag (xtlvld in register oscxcn) is set to ?1? by hardware when the external o scillator is settled. to avoid reading a false xtlvld, in crystal mode so ftware should delay at least 1 ms between enabling the external oscillator and checking xtlvld. rc and c modes typically require no startup time. the clksl[1:0] bits in register cl ksel select which osc illator source is used as the system clock. clksl[1:0] must be set to 01b for the system clock to run from th e external oscillator; however the exter - nal oscillator may still clock certain per ipherals (timers, pca) when the inte rnal oscillator is selected as the system clock. the system clock may be switched on-the-fly be tween the intern al oscillator, external oscilla - tor, and clock multiplier so long as the selected clock source is enabled and has settled. sfr definition 17.5. clksel: clock select bits7?2: unused. read = 000000b; write = don?t care. bits1?0: clksl1?0: system clock select these bits select the system clock source. r r r r r r r/w r/w reset value ? ? ? ? ? ? clksl 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa9 clksl selected clock 00 internal oscillator (a s determined by the ifcn bits in register oscicn) 01 external oscillator 10 clock multiplier 11 reserved table 17.1. oscillator electri cal characteristics ?40 to +85 c unless otherwise specified parameter conditions min typ max units internal oscillator frequency reset frequency 24 24.5 25 mhz internal oscillator supply current (from v dd ) oscicn.7 = 1 450 a
c8051f350/1/2/3 rev. 1.0 137 18. port input/output digital and analog resources are available through 17 i/o pins. port pins are organized as two byte-wide ports and one 1-bit port. each of the port pins can be defined as general-purpose i/o (gpio) or analog input/output; port pins p0.0 - p1.7 can be assigned to one of the internal digital resources as shown in figure 18.3 . the designer has complete control over which functions are assigned, limited only by the number of physical i/o pins. this re source assignment flexibility is achi eved through the use of a priority crossbar decoder. note that the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital reso urces to the i/o pins based on the priority decoder ( figure 18.3 and figure 18.4 ). the registers xbr0 and xbr1, defined in sfr definition 18.1 and sfr definition 18.2 , are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 18.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port output mode registers (pnmdout, where n = 0,1,2). com - plete electrical spec ifications for port i/o are given in ta b l e 18.1 on page 150 . xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 pnmdout, pnmdin registers uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 4 pca 4 spi cp0 outputs 2 p1 i/o cells p1.0 p1.7 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 p2 (p2.0) p2 i/o cell p2.0 figure 18.1. port i/o fun ctional block diagram
gnd /port-outenable port-output push-pull vdd vdd /weak-pullup (weak) port pad analog input analog select port-input c8051f350/1/2/3 138 rev. 1.0 figure 18.2. port i/o cell block diagram
c8051f350/1/2/3 rev. 1.0 139 18.1. priority crossbar decoder the priority crossb ar decoder (figure 18.3) assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the leas t-significant unassigned port pin is assigned to that resource (excluding uart0, which will be assigned to pins p0.4 and p0.5, and the comparator 0 outputs, which will be assigned to p1.4 and p1.5). if a port pin is assigned, the crossb ar skips that pin when assigning the next selected resource. additionally, the crossbar will skip port pins whose associated bits in the pnskip registers are set. the pnskip registers allow so ftware to skip port pins that are to be used for analog input, dedicate d functions, or gpio. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to p0.3 and/or p0.2 for the external oscillator, p0.6 for the external cnvstr signal, p1.6 for ida0, p1.7 for ida1, and any selected adc or comparator inputs. the crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. figure 18.3 shows the crossbar decoder priority with no port pins skipped (p0skip, p1skip = 0x00); figure 18.4 shows the crossbar decoder priority with the xtal1 (p0.2) and xtal2 (p0.3) pins skipped (p0skip = 0x0c). p2 x1 x2 cnvstr ida0 ida1 01234567012345670 (*4-wire spi only) /sysclk cex0 cex1 cex2 eci 0000000000000000 p1skip[0:7] sda special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially assignable to peripheral sf signals t1 p0skip[0:7] scl tx0 cp0a cp0 t0 p0 p1 nss* sck miso mosi rx0 sf signal s pin i/o figure 18.3. crossbar priority decoder with no pins skipped
p2 x1 x2 cnvstr ida0 ida1 01234567012345670 (*4-wire spi only) /sysclk cex0 cex1 cex2 eci 0011000000000000 p0 p1 miso cp0a cp0 sck rx0 sf signal s pin i/o tx0 sda mosi nss* scl special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially assignable to peripheral sf signals t1 p0skip[0:7] t0 p1skip[0:7] c8051f350/1/2/3 140 rev. 1.0 figure 18.4. crossbar priority d ecoder with crystal pins skipped registers xbr0 and xbr1 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assi gns both pins associated with the smbus (sda and scl); when the uart is selected, the crossbar assign s both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for bootloading purp oses: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. co mparator outputs are also fixed: cp0a will appear only on p1.4, cp0 will appear only on p1.5. standar d port i/os appear cont iguously after the priori tized functions have been assigned. important note: the spi can be operated in either 3-wire or 4-wire modes, pending the state of the nssmd1?nssmd0 bits in register spi0cn. according to the spi mode, the nss signal may or may not be routed to a port pin.
c8051f350/1/2/3 rev. 1.0 141 18.2. port i/o initialization port i/o initialization cons ists of the following steps: step 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). step 2. select the output mode (open-drain or push -pull) for all port pins, using the port output mode register (pnmdout). step 3. select any pins to be skipped by the i/o crossbar using the port skip registers (pnskip). step 4. assign port pins to desired peripherals. step 5. enable the cr ossbar (xbare = ?1?). all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver are disabled. this process saves power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. additionally, all analog input pins should be configur ed to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a ?1? indicates a digital input, and a ?0? indicates an analog input. all pins default to digital inputs on reset. see sfr defini - tion 18.4 for the pnmdin register details. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd - out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bi t in xbr1 is ?0?, a we ak pull-up is enabled for all port i/o con - figured as open-drain. weakpud does not affect the pu sh-pull port i/o. furthermo re, the weak pull-up is turned off on an output that is driving a ?0? to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the approp riate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to ?1? enables the cross bar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out us ing the priority decode ta b l e . the crossbar must be enabled to us e port pins as standard port i/o in output mode. port output drivers are disabled while the crossbar is disabled.
c8051f350/1/2/3 142 rev. 1.0 sfr definition 18.1. xbr0: port i/o cro ssbar register 0 bits7?6: unused. read = 00b, write = don?t care. bit5: cp0ae: comparator0 asynchronous output enable 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin p1.4. bit4: cp0e: comparator0 output enable 0: cp0 unavailable at port pin. 1: cp0 routed to port pin p1.5. bit3: syscke: /sysclk output enable 0: /sysclk unavaila ble at port pin. 1: /sysclk output r outed to port pin. bit2: smb0e: smbus i/o enable 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. bit1: spi0e: spi i/o enable 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that t he spi can be assigned either 3 or 4 gpio pins. bit0: urt0e: uart i/o output enable 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5. r r r/w r/w r/w r/w r/w r/w reset value ? ? cp0ae cp0e syscke smb0e spi0e urt0e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe1
c8051f350/1/2/3 rev. 1.0 143 sfr definition 18.2. xbr1: port i/o cro ssbar register 1 bit7: weakpud: port i/o weak pull-up disable. 0: weak pull-ups enabled (except for ports whose i/o are configured as analog input). 1: weak pull-ups disabled. bit6: xbare: cros sbar enable. 0: crossbar disabled. 1: crossbar enabled. bit5: t1e: t1 enable 0: t1 unavailable at port pin. 1: t1 routed to port pin. bit4: t0e: t0 enable 0: t0 unavailable at port pin. 1: t0 routed to port pin. bit3: ecie: pca0 exter nal counter input enable 0: eci unavailable at port pin. 1: eci routed to port pin. bit2: unused. read = 0b. write = don?t care. bits1?0: pca0me: pca module i/o enable bits. 00: all pca i/o unavailable at port pins. 01: cex0 routed to port pin. 10: cex0, cex1 routed to port pins. 11: cex0, cex1, cex2 routed to port pins. r/w r/w r/w r/w r/w r r/w r/w reset value weakpud xbare t1e t0e ecie ? pca0me 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe2
c8051f350/1/2/3 144 rev. 1.0 18.3. general purpose port i/o port pins that remain unassigned by the crossbar and are not used by analog peripherals can be used for general purpose i/o. ports p0?p2 are accessed throug h corresponding special function registers (sfrs) that are both byte addressable and bit addressable. wh en writing to a port, the va lue written to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corres ponding port i/o pin). the exception to this is the execution of the read-modify-write instructions that ta rget a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the following: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the de stination is an individual bit in a port sfr. for these instructions, the value of the register (not the pin) is read, modified, and written back to the sfr.
c8051f350/1/2/3 rev. 1.0 145 sfr definition 18.3. p0: port0 bits7?0: p0.[7:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p0mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p0mdin. directly reads port pin when configured as digital input. 0: p0.n pin is logic low. 1: p0.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x80 sfr definition 18.4. p0mdin: port0 input mode bits7?0: analog input configuration bits for p0.7?p0.0 (respectively). port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is co nfigured as an analog input. 1: corresponding p0.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf1
c8051f350/1/2/3 146 rev. 1.0 sfr definition 18.5. p0mdout: port0 output mode bits7?0: output configuration bits for p0.7?p0.0 (res pectively): ignored if corresponding bit in regis- ter p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. (note: when sda and scl appear on any of the port i/o, each are open-drain regardless of the value of p0mdout). r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa4 sfr definition 18.6. p0skip: port0 skip bits7?0: p0skip[7:0]: port0 cr ossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd4
c8051f350/1/2/3 rev. 1.0 147 sfr definition 18.7. p1: port1 bits7?0: p1.[7:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p1mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p1mdin. directly reads port pin when configured as digital input. 0: p1.n pin is logic low. 1: p1.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x90 sfr definition 18.8. p1mdin: port1 input mode bits7?0: analog input configuration bits for p1.7?p1.0 (respectively). port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is co nfigured as an analog input. 1: corresponding p1.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf2
c8051f350/1/2/3 148 rev. 1.0 sfr definition 18.9. p1mdout: port1 output mode bits7?0: output configuration bits for p1.7?p1.0 (res pectively): ignored if corresponding bit in regis- ter p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa5 sfr definition 18.10. p1skip: port1 skip bits7?0: p1skip[7:0]: port1 cr ossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd5
c8051f350/1/2/3 rev. 1.0 149 sfr definition 18.11. p2: port2 bits7?1: unused. read = 0000000b. write = don?t care. bit0: p2.0 write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p2mdout.n bit = 0). read - directly reads port pin. 0: p2.n pin is logic low. 1: p2.n pin is logic high. rrrrrrrr/wreset value ? ? ? ? ? ? ? p2.0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xa0 sfr definition 18.12. p2mdout: port2 output mode bits7?1: unused. read = 0000000b. write = don?t care. bit0: output configuration bit for p2.0. 0: p2.0 output is open-drain. 1: p2.0 output is push-pull. rrrrrrrr/wreset value ? ? ? ? ? ? ? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa6
table 18.1. port i/o dc electri cal characteristics c8051f350/1/2/3 150 rev. 1.0 v dd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull v dd ? 0.7 v dd ? 0.1 v dd ? 0.8 v output low voltage i ol = 8.5 ma i ol = 10 a i ol = 25 ma 1.0 0.6 0.1 v input high voltage 2.0 v input low voltage 0.8 v input leakage cur- rent weak pull-up off weak pull-up on, v in = 0 v 25 1 50 a
c8051f350/1/2/3 rev. 1.0 151 19. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i2c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonom ously controlling the serial transfer of the data. data can be transferre d at up to 1/10th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple mas - ters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and gene ration. three sfrs are associated with the smbus: smb0cf configures the sm bus; smb0cn controls the status of the smbus; and smb0dat is the data register, used for both transmitting and receiving smbus data and slave addresses. data path control smbus control logic c r o s s b a r scl filter n sda control scl control arbitration scl synchronization irq generation scl generation (master mode) sda control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n figure 19.1. smbus block diagram
c8051f350/1/2/3 152 rev. 1.0 19.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i2c-bus and how to use it (including specifications), philips semiconductor. 2. the i2c-bus specification -- ve rsion 2.0, philips semiconductor. 3. system management bus specification -- version 1.1, sbs implementers forum. 19.2. smbus configuration figure 19.2 shows a typical smbus configuration. the sm bus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-direc - tional scl (serial clock) and sda (serial data) lines mu st be connected to a positive power supply voltage through a pull-up resistor or similar circuit. every devic e connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sd a scl figure 19.2. typical smbus configuration 19.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitr ation. note that it is not necessary to specify one device as the master in a system ; any device who transmits a star t and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more byte s of data, and a stop condition. each byte that is received (by a master or slave) must be acknow ledged (ack) with a low sda during a high scl (see figure 19.3 ). if the receiving device does not ack, the transmitting devi ce will read a nack (not acknowl - edge), which is a high sda during a high scl.
c8051f350/1/2/3 rev. 1.0 153 the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and direction bit. if the trans - action is a write operation from the master to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 19.3 illustrates a typical smbus transaction. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop figure 19.3. smbus transaction 19.3.1. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?19.3.4. scl high (smbus free) timeout? on page 154 ). in the event that two or more devices attemp t to begin a transfer at the same time, an arbi - tration scheme is employed to force one master to gi ve up the bus. the master devices continue transmit - ting until one attempts a high wh ile the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attemp ting the high will detect a low sda and lose the arbitration. the win - ning master continues its transmission without inte rruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destructive: one device always wins, and no data is lost.
c8051f350/1/2/3 154 rev. 1.0 19.3.2. clock low extension smbus provides a clock synchronizati on mechanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 19.3.3. scl low timeout if the scl line is held low by a slave device on the bus , no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi - cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to reload when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to overflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. 19.3.4. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods. if the smbus is waiting to generate a master start, the start will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave-only implementation.
c8051f350/1/2/3 rev. 1.0 155 19.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con - trol for serial transfers; higher level protocol is dete rmined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as define d by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information smbus interrupts are generated for each data byte or slave address that is transf erred. when transmitting, this interrupt is generated after the ack cycle so th at software may read the received ack value; when receiving data, this interrupt is generated before t he ack cycle so that software may define the outgoing ack value. see section ?19.5. smbus transfer modes? on page 163 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus inte rrupt. the smb0cn register is described in section ?19.4.2. smb0cn control register? on page 159 ; table 19.4 provides a quick smb0cn decoding refer - ence. smbus configuration options include: ? timeout detection (scl low timeout and/or bus free timeout) ? sda setup and hold time extensions ? slave event enable/disable ? clock source selection these options are selected in the smb0cf register, as described in section ?19.4.1. smbus configura - tion register? on page 156 .
c8051f350/1/2/3 156 rev. 1.0 19.4.1. smbus configuration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options . when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). table 19.1. smbus clock source selection the smbcs1?0 bits select the smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when op erating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 19.1 . note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uart baud rates simultaneously. timer configuration is covered in section ?22. timers? on page 195 . t highmin t lowmin 1 f clocksourceoverflow ---------------- ------------------ ----------- - == equation 19.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 19.1 . when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typica l smbus bit rate is approximated by equation 19.2 . bitrate f clocksourceoverflow 3 --------------- ----------------- ------------- - = equation 19.2. typical smbus bit rate smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow
c8051f350/1/2/3 rev. 1.0 157 figure 19.4 shows the typical scl generation described by equation 19.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will never exce ed the limits defined by equation equation 19.1 . scl timer source overflows scl high timeout t low t high figure 19.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. ta b l e 19.2 shows the min - imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. table 19.2. minimum sda setup and hold times *note: setup time for ack bit transmissions and the msb of all data transfers. the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same wr ite that defines the ou tgoing ack value, s/w delay is zero. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section ?19.3.3. scl low timeout? on page 154 ). the smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count when scl is low. the timer 3 interrupt service rou - tine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is set, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 19.4 ). when a free timeout is dete cted, the interface will respond as if a stop was detected (an interrupt will be generat ed, and sto will be set). exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay* 3 system clocks 1 11 system clocks 12 system clocks
c8051f350/1/2/3 158 rev. 1.0 sfr definition 19.1. smb0cf: smbus clock/configuration bit7: ensmb: smbus enable. this bit enables/disables the smbus interface. when enabled, the interface constantly mon- itors the sda and scl pins. 0: smbus interface disabled. 1: smbus interface enabled. bit6: inh: smbus slave inhibit. when this bit is set to logic 1, the smbus does not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 0: smbus slave mode enabled. 1: smbus slave mode inhibited. bit5: busy: smbus busy indicator. this bit is set to logic 1 by hardware when a tran sfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. bit4: exthold: smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to table 19.2. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. bit3: smbtoe: smbus scl ti meout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. if timer 3 is con- figured in split mode (t3split is set), only the high byte of ti mer 3 is held in reload while scl is high. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus communication. bit2: smbfte: smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 smbus cl ock source periods. bits1?0: smbcs1?smbcs0: smbu s clock source selection. these two bits select the smbus clock source , which is used to generate the smbus bit rate. the selected device should be configured according to equation 19.1. r/w r/w r r/w r/w r/w r/w r/w reset value ensmb inh busy exthold smbtoe sm bfte smbcs1 smbcs0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc1 smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow
c8051f350/1/2/3 rev. 1.0 159 19.4.2. smb0cn control register smb0cn is used to control the interface and to provid e status information (see sfr definition 19.2). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master and txmode indi cate the master/slave state and transmit/receive modes, respectively. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas - ter. writing a ?1? to sta will cause the smbus interfac e to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardware after the start is generated). writing a ?1? to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received on the last ack cycle. ackrq is set each time a byte is received, indicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if so ftware does not write the ack bit before clearing si. sda will reflec t the defined ack value immediately following a write to the ack bit; however scl will remain low un til si is cleared. if a received slave address is not acknowledged, further slave events will be ignored unt il the next start is detected. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitratio n while operating as a slave indicates a bus error condi - tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginnin g and end of each transfer, after each byte frame, or when an arbitration is lost; see ta b l e 19.3 for more details. important note about the si bit: the smbus interface is st alled while si is set; th us scl is held low, and the bus is stalled until software clears si. ta b l e 19.3 lists all sources for hardware changes to the smb0cn bits. refer to table 19.4 for smbus sta - tus decoding using the smb0cn register.
c8051f350/1/2/3 160 rev. 1.0 sfr definition 19.2. smb0cn: smbus control bit7: master: smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. bit6: txmode: smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. bit5: sta: smbus start flag. write: 0: no start generated. 1: when operating as a master, a start condition is transmitted if the bus is free (if the bus is not free, the start is transmitted after a st op is received or a timeout is detected). if sta is set by software as an active mast er, a repeated start will be generated after the next ack cycle. read: 0: no start or repeated start detected. 1: start or repeated start detected. bit4: sto: smbus stop flag. write: 0: no stop condition is transmitted. 1: setting sto to logic 1 causes a stop condi tion to be transmitted after the next ack cycle. when the stop condition is generated, hardware clears sto to logic 0. if both sta and sto are set, a stop condition is transmitted followed by a start condition. read: 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). bit3: ackrq: smbus ac knowledge request this read-only bit is set to logic 1 when the smbus has received a byte and needs the ack bit to be written with the correct ack response value. bit2: arblost: smbus arbitration lost indicator. this read-only bit is set to logic 1 when the smbus loses arbitration while operating as a transmitter. a lost arbitration while a slave indicates a bus error condition. bit1: ack: smbus acknowledge flag. this bit defines the out-going ack level and re cords incoming ack leve ls. it should be writ- ten each time a byte is rece ived (when ackrq=1), or read after each byte is transmitted. 0: a "not acknowledge" has bee n received (if in transmitter mode) or will be transmitted (if in receiver mode). 1: an "acknowledge" has been re ceived (if in transmitter mode) or will be transmitted (if in receiver mode). bit0: si: smbus interrupt flag. this bit is set by hardware under the conditions listed in table 19.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. r r r/w r/w r r r/w r/w reset value master txmode sta sto ackrq arblost ack si 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xc0
table 19.3. sources for hardware changes to smb0cn ? a start is generated. ? a stop is generated. ? arbitration is lost. ? start is generated. ? smb0dat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smb0dat is not written before the start of an smbus frame. ? a start followed by an address byte is received. ? must be cleared by software. ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ? a byte has been received and an ack response value is needed. ? after each ack cycle. ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low while attempting to gener - ate a stop or repeated start condition. ? sda is sensed low while transmitting a ?1? (excluding ack bits). ? each time si is cleared. ? the incoming ack value is low (acknowl - edge). ? the incoming ack value is high (not acknowledge). ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software. c8051f350/1/2/3 rev. 1.0 161 bit set by hardware when: cleared by hardware when: master txmode sta sto ackrq arblost ack si
c8051f350/1/2/3 162 rev. 1.0 19.4.3. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi - tration, the transition from master transmitter to slave receiver is made with the correct data or address in smb0dat. sfr definition 19.3. smb0dat: smbus data bits7?0: smb0dat: smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial inter- face or a byte that has just been received on the smbus serial interface. the cpu can read from or write to this register whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu should not atte mpt to access this register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc2
c8051f350/1/2/3 rev. 1.0 163 19.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames; however, note that the inte rrupt is generated before the ack cycle when operat - ing as a receiver, and after the ack cycle when operating as a transmitter. 19.5.1. master transmitter mode serial data is transmitted on sda while the serial cl ock is output on scl. the smbus interface generates the start condition and transmits the first byte cont aining the address of the target slave and the data direction bit. in this case the da ta direction bit (r/w) will be logic 0 (write). the master then transmits one or more bytes of serial data. after each byte is transmitted, an acknowled ge bit is generated by the slave. the transfer is en ded when the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written follo wing a master transmitter interrupt. figure 19.5 shows a typical master transmitter sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that the ?data byte transferred? interrupts occur after the ack cycle in this mode. a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 19.5. typical mast er transmitter sequence
c8051f350/1/2/3 164 rev. 1.0 19.5.2. master receiver mode serial data is received on sda while the serial clock is output on scl. the smbus interface generates the start condition and transmits the first byte containing the address of the target slave and the data direc - tion bit. in this case the da ta direction bit (r/w) will be logic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. after each byte is received, ackrq is set to ?1? and an interrupt is generated. software must write the ack bit (smb0cn.1) to define the outgoing ackno wledge value (note: writing a ?1? to the ack bit gen - erates an ack; writing a ?0? genera tes a nack). software should write a ?0? to the ack bit after the last byte is received, to transmit a na ck. the interface exits master receiver mode after the sto bit is set and a stop is generated. note that the interface will switch to master tr ansmitter mode if smb0dat is written while an active master receiver. figure 19.6 shows a typical master rece iver sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 19.6. typical m aster receiver sequence
c8051f350/1/2/3 rev. 1.0 165 19.5.3. slave receiver mode serial data is received on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direction bit (write in this case) is received. upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the rece ived slave address is ignored, slav e interrupts will be inhibited until the next start is detected. if the received slave addr ess is acknowledged, zero or more data bytes are received. software must write the ack bit after each received byte to ack or nack the received byte. the interface exits slave receiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0 dat is written while an active slave receiver. figure 19.7 shows a typical slave receiver sequence. two received data bytes are show n, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 19.7. typical sl ave receiver sequence
c8051f350/1/2/3 166 rev. 1.0 19.5.4. slave transmitter mode serial data is transmitted on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to re ceive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. upon entering slave transmitter mode, an interrupt is generated and the ackr q bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a na ck. if the received slave address is ignored, slave interrupts will be inhibited un til a start is detected. if the received slave address is acknowledged, data should be written to smb0dat to be transmitted. the interface enters slave transmitter mode, and trans - mits one or more bytes of data. after each byte is tr ansmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be writt en with the next data byte. if the acknowledge bit is a nack, smb0dat should not be written to before si is cleared (note: an error condition may be gener - ated if smb0dat is written following a received nack while in slave transmitter mode). the interface exits slave transmitter mode after receiving a stop. no te that the interface will sw itch to slave receiver mode if smb0dat is not written fo llowing a slave tran smitter interrupt. figure 19.8 shows a typical slave transmitter sequence. two transmitted data bytes ar e shown, though any number of bytes may be trans - mitted. notice that the ?data byte transferred? interrupts occur after the ack cycle in this mode. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 19.8. typical sl ave transmitter sequence
c8051f350/1/2/3 rev. 1.0 167 19.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. in the table below, status vector refers to the four upper bits of smb0cn : master, txmode, sta, and sto. note that the shown response options are only the typical response s; application-specific pr ocedures are allowed as long as they conform to the smbus specification. hig hlighted responses are allowed but do not conform to the smbus specification. table 19.4. smbus status decoding mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0dat. 0 0 x 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x abort transfer. 0 1 x 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 0 0 x end transfer with stop. 0 1 x end transfer with stop and start another transfer. 1 1 x send repeated start. 1 0 x switch to master receiver mode (clear si without writ - ing new data to smb0dat). 0 0 x
c8051f350/1/2/3 168 rev. 1.0 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 send nack to indicate last byte, and send stop. 0 1 0 send nack to indicate last byte, and send stop fol - lowed by start. 1 1 0 send ack followed by repeated start. 1 0 1 send nack to indicate last byte, and send repeated start. 1 0 0 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 send nack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 0 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expect - ing stop condition). 0 0 x 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 01x a slave byte was transmitted; error detected. no action required (expect - ing master to end transfer). 0 0 x 0101 0 x x a stop was detected while an addressed slave transmitter. no action required (transfer complete). 0 0 x table 19.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack
c8051f350/1/2/3 rev. 1.0 169 slave receiver 0010 10x a slave address was received; ack requested. acknowledge received address. 0 0 1 do not acknowledge received address. 0 0 0 11x lost arbitration as master; slave address received; ack requested. acknowledge received address. 0 0 1 do not acknowledge received address. 0 0 0 reschedule failed transfer; do not acknowledge received address. 1 0 0 0010 0 1 x lost arbitration while attempting a repeated start. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 0001 11x lost arbitration while attempting a stop. no action required (transfer complete/aborted). 0 0 0 00x a stop was detected while an addressed slave receiver. no action required (transfer complete). 0 0 x 01x lost arbitration due to a detected stop. abort transfer. 0 0 x reschedule failed transfer. 1 0 x 0000 10x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 do not acknowledge received byte. 0 0 0 11x lost arbitration while transmitting a data byte as master. abort failed transfer. 0 0 0 reschedule failed transfer. 1 0 0 table 19.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack
c8051f350/1/2/3 170 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 171 20. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?20.1. enhanced baud rate generation? on page 172 ). received data buffering allows uart0 to start reception of a second incoming data byte before software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generate d each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart 0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set q d clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch) figure 20.1. uart0 block diagram
c8051f350/1/2/3 172 rev. 1.0 20.1. enhanced baud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 20.2 ), which is not user- accessible. both tx and rx timer overflows are divid ed by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is de tected on the rx pin. th is allows a receive to begin any time a start is detected, independent of the tx timer state. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart figure 20.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?22.1.3. mode 2: 8-bit counter/timer with auto-reload? on page 197 ). the timer 1 reload value should be set so that over - flows will occur at two times the desired ua rt baud rate frequency. note that timer 1 may be clocked by one of six source s: sysclk, sysclk / 4, sysclk / 12, sysclk / 48, the external oscillator clock / 8, or an external input t1. the uart0 baud rate is determined by equation 20.1 -a and equation 20.1 -b. uartbaudrate 1 2 -- - t1_overflow_rate = t1_overflow_rate t1 clk 256 th1 ? ------------ ------------- - = a) b) equation 20.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as described in section ?22. timers? on page 195 . a quick reference for typical baud rates and system clock frequencies is given in ta b l e 20.1 through table 20.6 . note that the internal os cillator may still genera te the system clock wh en the external oscillator is driving timer 1.
c8051f350/1/2/3 rev. 1.0 173 20.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown below. or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx figure 20.3. uart interconnect diagram 20.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin a nd received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en software writes a data byte to th e sbuf0 register. the ti0 transmit inter - rupt flag (scon0.1) is set at the end of the transmi ssion (the beginning of the stop-bit time). data recep - tion can begin any time after the ren0 rece ive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over - run, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space figure 20.4. 8-bit u art timing diagram
c8051f350/1/2/3 174 rev. 1.0 20.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma - ble ninth data bit, and a stop bit. the state of the nint h transmit data bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg - ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive en able bit (scon0.4) is set to ?1?. after the stop bit is received, the data byte will be lo aded into the sbuf0 receiv e register if the followin g conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these cond itions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to ?1?. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to ?1?. a ua rt0 interrupt will occur if enabled when either ti0 or ri0 is set to ?1?. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 figure 20.5. 9-bit u art timing diagram 20.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor co nfigures its uart such that when a stop bit is received, the uart will gener ate an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address byte has been received. in the ua rt interrupt handler, software will compare the received address with the slave's own assigned 8-bit addre ss. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addres sed slave resets its mce0 bit to ignore all transmis - sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s).
master device slave device tx rx rx tx slave device rx tx slave device rx tx v+ c8051f350/1/2/3 rev. 1.0 175 figure 20.6. uart multi-processor mode interconnect diagram
c8051f350/1/2/3 176 rev. 1.0 sfr definition 20.1. scon0: serial port 0 control bit7: s0mode: serial port 0 operation mode. this bit selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. bit6: unused. read = 1b . write = don?t care. bit5: mce0: multiprocessor communication enable. the function of this bit is dependent on the serial port 0 operation mode. s0mode = 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. s0mode = 1: multiprocesso r communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is generated only when the ninth bit is logic 1. bit4: ren0: receive enable. this bit enables/disables the uart receiver. 0: uart0 reception disabled. 1: uart0 reception enabled. bit3: tb80: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmission bit in 9-bit uart mode. it is not used in 8-bit uart mode. set or cleared by software as required. bit2: rb80: ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. bit1: ti0: transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8- bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. bit0: ri0: receive interrupt flag. set to ?1? by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enab led, setting this bit to ?1? causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by soft- ware. r/w r r/w r/w r/w r/w r/w r/w reset value s0mode ? mce0 ren0 tb80 rb80 ti0 ri0 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x98
c8051f350/1/2/3 rev. 1.0 177 sfr definition 20.2. sbuf0: serial (uart0 ) port data buffer bits7?0: sbuf0[7:0]: serial data buffer bits 7?0 (msb?lsb) this sfr accesses two registers; a transmit shif t register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is he ld for serial transmis- sion. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the con- tents of the receive latch. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x99
table 20.1. timer settings for standard baud rates using the internal oscillator sysclk from internal osc. *note: sca1?sca0 and t1m bit definitions can be found in section 22.1 . table 20.2. timer settings for standard baud rates using an external 25.0 mhz oscillator sysclk from external osc. sysclk from internal osc. *note: sca1?sca0 and t1m bit definitions can be found in section 22.1 . c8051f350/1/2/3 178 rev. 1.0 frequency: 24.5 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select)* t1m* timer 1 reload value (hex) 230400 ?0.32% 106 sysclk xx 1 0xcb 115200 ?0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 ?0.32% 848 sysclk / 4 01 0 0x96 14400 0.15% 1704 sysclk / 12 00 0 0xb9 9600 ?0.32% 2544 sysc lk / 12 00 0 0x96 2400 ?0.32% 10176 sysc lk / 48 10 0 0x96 1200 0.15% 20448 sysclk / 48 10 0 0x2b x = don?t care frequency: 25.0 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select)* t1m* timer 1 reload value (hex) 230400 ?0.47% 108 sysclk xx 1 0xca 115200 0.45% 218 sysclk xx 1 0x93 57600 ?0.01% 434 sysclk xx 1 0x27 28800 0.45% 872 sysclk / 4 01 0 0x93 14400 ?0.01% 1736 sysclk / 4 01 0 0x27 9600 0.15% 2608 extclk / 8 11 0 0x5d 2400 0.45% 10464 sysclk / 48 10 0 0x93 1200 ?0.01% 20832 sysclk / 48 10 0 0x27 57600 ?0.47% 432 extclk / 8 11 0 0xe5 28800 ?0.47% 864 extclk / 8 11 0 0xca 14400 0.45% 1744 extclk / 8 11 0 0x93 9600 0.15% 2608 extclk / 8 11 0 0x5d x = don?t care
table 20.3. timer settings for standard baud rates using an external 22.1184 mhz oscillator sysclk from external osc. sysclk from internal osc. *note: sca1?sca0 and t1m bit definitions can be found in section 22.1 . table 20.4. timer settings for standard baud rates using an external 18.432 mhz oscillator sysclk from external osc. sysclk from internal osc. *note: sca1?sca0 and t1m bit definitions can be found in section 22.1 . c8051f350/1/2/3 rev. 1.0 179 frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select)* t1m* timer 1 reload value (hex) 230400 0.00% 96 sysclk xx 1 0xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysclk / 48 10 0 0x40 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 x = don?t care frequency: 18.432 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select)* t1m* timer 1 reload value (hex) 230400 0.00% 80 sysclk xx 1 0xd8 115200 0.00% 160 sysclk xx 1 0xb0 57600 0.00% 320 sysclk xx 1 0x60 28800 0.00% 640 sysclk / 4 01 0 0xb0 14400 0.00% 1280 sysclk / 4 01 0 0x60 9600 0.00% 1920 sysclk / 12 00 0 0xb0 2400 0.00% 7680 sysclk / 48 10 0 0xb0 1200 0.00% 15360 sysclk / 48 10 0 0x60 230400 0.00% 80 extclk / 8 11 0 0xfb 115200 0.00% 160 extclk / 8 11 0 0xf6 57600 0.00% 320 extclk / 8 11 0 0xec 28800 0.00% 640 extclk / 8 11 0 0xd8 14400 0.00% 1280 extclk / 8 11 0 0xb0 9600 0.00% 1920 extclk / 8 11 0 0x88 x = don?t care
table 20.5. timer settings for standard baud rates using an external 11.0592 mhz oscillator sysclk from external osc. sysclk from internal osc. *note: sca1?sca0 and t1m bit definitions can be found in section 22.1 . table 20.6. timer settings for standard baud rates using an external 3.6864 mhz oscillator sysclk from external osc. sysclk from internal osc. *note: sca1?sca0 and t1m bit definitions can be found in section 22.1 . c8051f350/1/2/3 180 rev. 1.0 frequency: 11.0592 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select)* t1m* timer 1 reload value (hex) 230400 0.00% 48 sysclk xx 1 0xe8 115200 0.00% 96 sysclk xx 1 0xd0 57600 0.00% 192 sysclk xx 1 0xa0 28800 0.00% 384 sysclk xx 1 0x40 14400 0.00% 768 sysclk / 12 00 0 0xe0 9600 0.00% 1152 sysclk / 12 00 0 0xd0 2400 0.00% 4608 sysclk / 12 00 0 0x40 1200 0.00% 9216 sysclk / 48 10 0 0xa0 230400 0.00% 48 extclk / 8 11 0 0xfd 115200 0.00% 96 extclk / 8 11 0 0xfa 57600 0.00% 192 extclk / 8 11 0 0xf4 28800 0.00% 384 extclk / 8 11 0 0xe8 14400 0.00% 768 extclk / 8 11 0 0xd0 9600 0.00% 1152 extclk / 8 11 0 0xb8 x = don?t care frequency: 3.6864 mhz target baud rate (bps) baud rate% error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select)* t1m* timer 1 reload value (hex) 230400 0.00% 16 sysclk xx 1 0xf8 115200 0.00% 32 sysclk xx 1 0xf0 57600 0.00% 64 sysclk xx 1 0xe0 28800 0.00% 128 sysclk xx 1 0xc0 14400 0.00% 256 sysclk xx 1 0x80 9600 0.00% 384 sysclk xx 1 0x40 2400 0.00% 1536 sysclk / 12 00 0 0xc0 1200 0.00% 3072 sysclk / 12 00 0 0x80 230400 0.00% 16 extclk / 8 11 0 0xff 115200 0.00% 32 extclk / 8 11 0 0xfe 57600 0.00% 64 extclk / 8 11 0 0xfc 28800 0.00% 128 extclk / 8 11 0 0xf8 14400 0.00% 256 extclk / 8 11 0 0xf0 9600 0.00% 384 extclk / 8 11 0 0xe8 x = don?t care
c8051f350/1/2/3 rev. 1.0 181 21. serial peripheral interface (spi0) the serial peripheral interface (spi0) provides acce ss to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple mas - ters and slaves on a single spi bus. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operat ion in a multi-master environment, avoiding conten - tion on the spi bus when more than one master atte mpts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional general pur - pose port i/o pins can be used to select multiple sl ave devices in master mode. sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien figure 21.1. spi block diagram
c8051f350/1/2/3 182 rev. 1.0 21.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 21.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat - ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 21.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat - ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 21.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen - erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 21.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave dev ice, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point-to-point communica tion between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-ma ster mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of th e nss signal disables the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssm d0 determines what logic leve l the nss pin will output. this configuration should only be used when operating spi0 as a master device. see figure 21.2, figure 21.3, and figure 21.4 for typical connection diag rams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ? 18. port input/output ? on page 137 for general purpose port i/o and crossbar information.
c8051f350/1/2/3 rev. 1.0 183 21.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers data to the spi master on th e miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit -complete and receive-data-ready flag. the data byte received from the slave is transferred msb-first into the master's shift regi ster. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another mast er is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) ar e set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an inte rrupt if enabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas - ter mode, slave devices can be addressed individua lly (if needed) using general-purpose i/o pins. figure 21.2 shows a connection diagram between two ma ster devices in mu ltiple-master mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 21.3 shows a connection diagram between a master dev ice in 3-wire master mode and a slave device. 4-wire single-master mode is active wh en nssmd1 (spi0cn.3) = 1. in this mode, nss is configured as an output pin, and can be used as a sl ave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit nssm d0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 21.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices.
master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss c8051f350/1/2/3 184 rev. 1.0 figure 21.2. multiple-master mode connect ion diagram figure 21.3. 3-wire single master and slave mode connection diagram figure 21.4. 4-wire single master and slave mode connection diagram
c8051f350/1/2/3 rev. 1.0 185 21.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig - nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted into the shift register, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initia te transfers. data to be transferred to the master device is pre-loaded into the shift register by writ ing to spi0dat. writes to spi0dat are double-buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the shift register already contains data, the spi will load the shift register with the tran smit buffer?s contents after the last sck edge of the ne xt (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabl ed when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of n ss. note that the nss sig - nal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 21.4 shows a connection diagram between two slav e devices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is not a way of uniquely addressing the device in 3-wire slave mo de, spi0 must be the only slave device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 21.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 21.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: note that all of the following bits must be cleared by software. 1. the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. 2. the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, a nd the transmit buffer will not be written.this fl ag can occur in all spi0 modes. 3. the mode fault flag modf (spi0cn.5) is set to logic 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logi c 0 to disable spi0 and allow another master device to access the bus. 4. the receive overrun flag rxovrn (spi0cn.4) is set to logic 1 when configured as a slave, and a transfer is completed while the receive buffer still holds an unread byte from a previous transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost.
c8051f350/1/2/3 186 rev. 1.0 21.5. serial clock timing four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0c fg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0 cn.0) when changing the clock phase or polarity. the clock and data line relationships are shown in figure 21.5 . the spi0 clock rate register (spi0c kr) as shown in sfr definition 21.3 controls the master mode serial clock frequency. this register is ignored when operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the s ystem clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial inpu t data synchronously with the slave?s system clock. sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi figure 21.5. data/clo ck timing relationship 21.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data re gister, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures.
c8051f350/1/2/3 rev. 1.0 187 sfr definition 21.1. spi0cfg: spi0 configuration bit 7: spibsy: spi busy (read only). this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). bit 6: msten: master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. bit 5: ckpha: spi0 clock phase. this bit controls the spi0 clock phase. 0: data centered on first edge of sck period.* 1: data centered on second edge of sck period.* bit 4: ckpol: spi0 clock polarity. this bit controls the spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. bit 3: slvsel: slave selected flag (read only). this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but ra ther a de-glitched version of the pin input. bit 2: nssin: nss instantaneous pin input (read only). this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. bit 1: srmt: shift register empty (valid in slave mode, read only). this bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. note: srmt = 1 when in master mode. bit 0: rxbmt: receive buffer empty (valid in slave mode, read only). this bit will be set to logic 1 when the receiv e buffer has be en read and contains no new information. if there is new inform ation available in the receive buffer that has not been read, this bit will return to logic 0. note: rxbmt = 1 when in master mode. *note: see table 21.1 for timing parameters. r r/w r/w r/w r r r r reset value spibsy msten ckpha ckpol slvsel nssin srmt rxbmt 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa1
c8051f350/1/2/3 188 rev. 1.0 sfr definition 21.2. spi0cn: spi0 control bit 7: spif: spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data trans fer. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt service routine. this bit is not automatically cleared by hardware. it must be cleared by software. bit 6: wcol: write collision flag. this bit is set to logic 1 by hardware (and gene rates a spi0 interrupt) to indicate a write to the spi0 data register was attempted while a data transfer was in progress. this bit is not automatically cleared by hardware. it must be cleared by software. bit 5: modf: mode fault flag. this bit is set to logic 1 by hardware (and ge nerates a spi0 interrupt) when a master mode collision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). this bit is not auto- matically cleared by hardware. it must be cleared by software. bit 4: rxovrn: receive overru n flag (slave mode only). this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when the receive buffer still holds unread da ta from a previous transfer and the la st bit of the curr ent transfer is shifted into the spi0 shift register. this bit is not automatically cleare d by hardware. it must be cleared by software. bits 3?2: nssmd1?nssmd0: slave select mode. selects between the following nss operation modes: (see section ?21.2. spi0 master mode operation? on page 183 and section ?21.3. spi0 slave mode operation? on page 185 ). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (defau lt). nss is always an input to the device. 1x: 4-wire single-master mode. nss signal is mapped as an ou tput from the device and will assume the value of nssmd0. bit 1: txbmt: transmit buffer empty. this bit will be set to logic 0 when new data ha s been written to the transmit buffer. when data in the transmit buffer is tr ansferred to the spi sh ift register, this bit will be set to logic 1, indicating that it is safe to writ e a new byte to the transmit buffer. bit 0: spien: spi0 enable. this bit enables/disables the spi. 0: spi disabled. 1: spi enabled. r/wr/wr/wr/wr/wr/w r r/wreset value spif wcol modf rxovrn nssmd1 nssmd0 txbmt spien 00000110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xf8
c8051f350/1/2/3 rev. 1.0 189 sfr definition 21.3. spi0ckr: spi0 clock rate bits 7?0: scr7?scr0: spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequ ency is a divided version of the system clock, and is given in th e following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, r/w r/w r/w r/w r/w r/w r/w r/w reset value scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa2 f sck 2000000 241 + () --------------- ----------- = f sck 200 khz = f sck sysclk 2 spi 0 ckr 1 + () --------------- ------------------ --------------- - =
c8051f350/1/2/3 190 rev. 1.0 sfr definition 21.4. spi0dat: spi0 data bits 7?0: spi0dat: spi0 transmit and receive data. the spi0dat register is used to transmit an d receive spi0 data. writing data to spi0dat places the data into the transmit buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa3
sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis c8051f350/1/2/3 rev. 1.0 191 figure 21.6. spi master timing (ckpha = 0) figure 21.7. spi master timing (ckpha = 1)
sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz c8051f350/1/2/3 192 rev. 1.0 figure 21.8. spi slave timing (ckpha = 0) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz figure 21.9. spi slave timing (ckpha = 1)
table 21.1. spi slave timing parameters parameter description min max units master mode timing* (see figure 21.6 and figure 21.7) t mckh sck high time 1 x t sysclk ns t mckl sck low time 1 x t sysclk ns t mis miso valid to sck sample edge 20 ns t mih sck sample edge to miso change 0 ns slave mode timing* (see figure 21.8 and figure 21.9) t se nss falling to first sck edge 2 x t sysclk ns t sd last sck edge to nss rising 2 x t sysclk ns t sez nss falling to miso valid 4 x t sysclk ns t sdz nss rising to miso high-z 4 x t sysclk ns t ckh sck high time 5 x t sysclk ns t ckl sck low time 5 x t sysclk ns t sis mosi valid to sck sample edge 2 x t sysclk ns t sih sck sample edge to mosi change 2 x t sysclk ns t soh sck shift edge to miso change 4 x t sysclk ns *note: t sysclk is equal to one perio d of the device system clock (sysclk) in ns. c8051f350/1/2/3 rev. 1.0 193
c8051f350/1/2/3 194 rev. 1.0 n otes :
c8051f350/1/2/3 rev. 1.0 195 22. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer fo r use with other device peripherals or for general purpose use. these timers can be used to measure ti me intervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of oper - ation. timer 2 and timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. timers 0 and 1 may be clocked by one of five sources, determined by the timer mode select bits (t1m? t0m) and the clock scale bits (sca1?sca0). the clock scale bits define a pre- scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 22.3 for pre-scaled cl ock selection). timer 0/1 may then be configured to use this pre-sc aled clock signal or th e system clock. timer 2 and timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counters. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre - quency of up to one-fourth the system clock's frequen cy can be counted. the input signal need not be peri - odic, but it must be held at a gi ven level for at least two full system clock cycles to ensure the level is properly sampled. 22.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer co ntrol register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts ca n be enabled by setting the et0 bit in the ie register ( section ?12.4. interrupt register descriptions? on page 107 ); timer 1 interrupts can be enabled by setting the et1 bit in the ie register ( section 12.4 ). both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1?t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 22.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operat e identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4?tl0.0. the three upper bits of tl0 (tl0.7?tl0 .5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf 0 (tcon.5) is set and an interrupt will occur if timer 0 interrupts are enabled. timer 0 and timer 1 modes: ti mer 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto- reload two 8-bit timers with auto-reload t wo 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
c8051f350/1/2/3 196 rev. 1.0 the c/t0 bit (tmod.2) selects the counter/timer's cloc k source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?18.1. priority crossbar decoder? on page 139 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 22.3 ). setting the tr0 bit (tcon.4) enables the timer when ei ther gate0 (tmod.3) is logic 0 or the input signal /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 12.5 ). setting gate0 to ?1? allows the timer to be controlled by the external input signal /int0 (see section ?12.4. interrupt register descriptions? on page 107 ), facilitating pulse width measurements. setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal /int1 is used with timer 1; the /int1 polari ty is defined by bit in1pl in register it01cf (see sfr definition 12.5 ). tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor figure 22.1. t0 mode 0 block diagram 22.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except th at the counter/timer registers use all 16 bits. the counter/timers are enabled and configured in mode 1 in the same manner as for mode 0. tr0 gate0 /int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 111enabled x = don't care
c8051f350/1/2/3 rev. 1.0 197 22.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 (tcon.5) is set and the co unter in tl0 is reloaded from th0. if timer 0 interrupts are enable d, an interrupt will oc cur when the tf0 flag is set. the reload va lue in th0 is not changed. tl0 must be initialized to the desired va lue before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal /int0 is active as defined by bit in0pl in register it01cf (see section ?12.5. external interrupts? on page 111 for details on the external input signals /int0 and /int1). tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 22.2. t0 mode 2 block diagram
c8051f350/1/2/3 198 rev. 1.0 22.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the counter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an external input signal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the time r 1 overflow flag tf1 on ov erflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operat ing in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and uart. while timer 0 is oper - ating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 22.3. t0 mode 3 block diagram
c8051f350/1/2/3 rev. 1.0 199 sfr definition 22.1. tcon: timer contro bit7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 1 interrupt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 0 interrupt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit3: ie1: external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 1 service routine if it1 = 1. when it1 = 0, this flag is set to ?1? when /int1 is active as defined by bit in1pl in register it01cf (see sfr definition 12.5). bit2: it1: interrupt 1 type select. this bit selects whether the configured /int1 in terrupt will be edge or le vel sensitive. /int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 12.5). 0: /int1 is level triggered. 1: /int1 is edge triggered. bit1: ie0: external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 0 service routine if it0 = 1. when it0 = 0, this flag is set to ?1? when /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 12.5). bit0: it0: interrupt 0 type select. this bit selects whether the configured /int0 in terrupt will be edge or le vel sensitive. /int0 is configured active low or high by the in0p l bit in register it01cf (see sfr definition 12.5). 0: /int0 is level triggered. 1: /int0 is edge triggered. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x88
c8051f350/1/2/3 200 rev. 1.0 sfr definition 22.2. tmod: timer mode bit7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. 1: timer 1 enabled only when tr1 = 1 and /int1 is active as defined by bit in1pl in regis- ter it01cf (see sfr definition 12.5). bit6: c/t1: counter/timer 1 select. 0: timer function: timer 1 incremented by clock defined by t1m bit (ckcon.4). 1: counter function: timer 1 incremented by high-to-low transitions on external input pin (t1). bits5?4: t1m1?t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. 1: timer 0 enabled only when tr0 = 1 and /int0 is active as defined by bit in0pl in regis- ter it01cf (see sfr definition 12.5). bit2: c/t0: counter/timer select. 0: timer function: timer 0 incremented by clock defined by t0m bit (ckcon.3). 1: counter function: timer 0 incremented by high-to-low transitions on external input pin (t0). bits1?0: t0m1?t0m0: timer 0 mode select. these bits select the timer 0 operation mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x89 t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 10 mode 2: 8-bit counter/timer with auto- reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 10 mode 2: 8-bit counter/timer with auto- reload 1 1 mode 3: two 8-bit counter/timers
c8051f350/1/2/3 rev. 1.0 201 sfr definition 22.3. ckcon: clock control bit7: t3mh: timer 3 hi gh byte clock select. this bit selects the clock supplied to the timer 3 high byte if timer 3 is configured in split 8- bit timer mode. t3mh is ignored if timer 3 is in any other mode. 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. bit6: t3ml: timer 3 lo w byte clock select. this bit selects the clock supplie d to timer 3. if timer 3 is c onfigured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. bit5: t2mh: timer 2 hi gh byte clock select. this bit selects the clock supplied to the timer 2 high byte if timer 2 is configured in split 8- bit timer mode. t2mh is ignored if timer 2 is in any other mode. 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. bit4: t2ml: timer 2 lo w byte clock select. this bit selects the clock supplie d to timer 2. if timer 2 is c onfigured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. bit3: t1m: timer 1 clock select. this select the clock source su pplied to timer 1. t1m is ignore d when c/t1 is set to logic 1. 0: timer 1 uses the clock defined by the prescale bits, sca1?sca0. 1: timer 1 uses the system clock. bit2: t0m: timer 0 clock select. this bit selects the clock source supplied to timer 0. t0m is ignored when c/t0 is set to logic 1. 0: counter/timer 0 uses the clock defined by the prescale bits, sca1?sca0. 1: counter/timer 0 uses the system clock. bits1?0: sca1?sca0: timer 0/1 prescale bits. these bits control the division of the clock su pplied to timer 0 and timer 1 if configured to use prescaled clock inputs. r/w r/w r/w r/w r/w r/w r/w r/w reset value t3mh t3ml t2mh t2ml t1m t0m sca1 sca0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8e sca1 sca0 prescaled clock 0 0 system clock divided by 12 0 1 system clock divided by 4 1 0 system clock divided by 48 1 1 external clock divided by 8 note: external clock divided by 8 is synchronized with the system clock.
c8051f350/1/2/3 202 rev. 1.0 sfr definition 22.4. tl0: timer 0 low byte bits 7?0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8a sfr definition 22.5. tl1: timer 1 low byte bits 7?0: tl1: timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8b sfr definition 22.6. th0: timer 0 high byte bits 7?0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8c sfr definition 22.7. th1: timer 1 high byte bits 7?0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8d
c8051f350/1/2/3 rev. 1.0 203 22.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 2 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 22.2.1. 16-bit timer with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is load ed into the timer 2 register as shown in figure 22.4 , and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generat ed on each timer 2 overflow. additiona lly, if timer 2 inte rrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len tmr2l overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 22.4. timer 2 16-bi t mode block diagram
c8051f350/1/2/3 204 rev. 1.0 22.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bi t timers (tmr2h and tmr2l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 22.5 . tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clo ck select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external cloc k select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled and tf2len (tmr2cn.5) is set, an interrupt is gener - ated each time either tmr2l or tmr2h overflows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2len tf2l tf2h t2xclk tr2 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 22.5. timer 2 8- bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk
c8051f350/1/2/3 rev. 1.0 205 sfr definition 22.8. tmr2cn: timer 2 control bit7: tf2h: timer 2 high byte overflow flag. set by hardware when the timer 2 high byte ov erflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0xff ff to 0x0000. when the timer 2 inte rrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. tf2h is not automatically cleared by hard ware and must be cleared by software. bit6: tf2l: timer 2 low byte overflow flag. set by hardware when the timer 2 low byte over flows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf2len is set and timer 2 interr upts are enabled. tf2l will set when the low byte overflow s regardless of the timer 2 mo de. this bit is not automat- ically cleared by hardware. bit5: tf2len: timer 2 low byte interrupt enable. this bit enables/disables timer 2 low byte in terrupts. if tf2len is set and timer 2 inter- rupts are enabled, an interrupt w ill be generated when the low byte of timer 2 overflows. this bit should be cleared when operating timer 2 in 16-bit mode. 0: timer 2 low byte interrupts disabled. 1: timer 2 low byte interrupts enabled. bit4: unused. read = 0b . write = don?t care. bit3: t2split: timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. bit2: tr2: timer 2 run control. this bit enables/disables timer 2. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is always enabled in this mode. 0: timer 2 disabled. 1: timer 2 enabled. bit1: unused. read = 0b . write = don?t care. bit0: t2xclk: timer 2 external clock select. this bit selects the external cl ock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external o scillator clock source for both time r bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ck con) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 external clock selection is the system clock divided by 12. 1: timer 2 external clock selection is the external clock divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf2h tf2l tf2len ? t2split tr2 ? t2xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xc8
c8051f350/1/2/3 206 rev. 1.0 sfr definition 22.9. tmr2rll: timer 2 relo ad register low byte bits 7?0: tmr2rll: timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xca sfr definition 22.10. tmr2rlh: timer 2 relo ad register high byte bits 7?0: tmr2rlh: timer 2 reload register high byte. the tmr2rlh holds the high byte of the reload value for timer 2. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcb sfr definition 22.11. tmr2l: timer 2 low byte bits 7?0: tmr2l: timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit mode, tmr2l contains the 8-bit low byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcc sfr definition 22.12. tmr2h timer 2 high byte bits 7?0: tmr2h: timer 2 high byte. in 16-bit mode, the tmr2h register contains t he high byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcd
c8051f350/1/2/3 rev. 1.0 207 22.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr3cn.3) defines the timer 3 operation mode. timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 3 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 22.3.1. 16-bit timer with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tm3rll) is load ed into the timer 3 register as shown in figure 22.6 , and the timer 3 high byte overflow flag (tmr3cn.7) is se t. if timer 3 interrupts ar e enabled, an interrupt will be generated each timer 3 overflow. additionally, if ti mer 3 interrupts are enabled and the tf3len bit is set (tmr3cn.5), an interrupt will be generated each time the lower 8 bi ts (tmr3l) overflow from 0xff to 0x00. external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split tf3l tf3h t3xclk tr3 0 1 t3xclk interrupt tf3len ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 22.6. timer 3 16-bi t mode block diagram
c8051f350/1/2/3 208 rev. 1.0 22.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 22.7 . tmr3rll holds the reload value for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 3 clo ck select bits (t3mh and t3ml in ckcon) select either sysclk or the clock defined by the timer 3 external cloc k select bit (t3xclk in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled (ie.5), an interrupt is generated each time tmr3h overflows. if timer 3 interrupts are enabled and tf3len (tmr3cn.5) is set, an interrupt is gener - ated each time either tmr3l or tmr3h overflows. when tf3len is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 t3xclk 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split tf3len tf3l tf3h t3xclk tr3 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 22.7. timer 3 8- bit mode block diagram t3mh t3xclk tmr3h clock source t3ml t3xclk tmr3l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk
c8051f350/1/2/3 rev. 1.0 209 sfr definition 22.13. tmr3cn: timer 3 control bit7: tf3h: timer 3 high byte overflow flag. set by hardware when the timer 3 high byte ov erflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0xff ff to 0x0000. when the timer 3 inte rrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. tf3h is not automatically cleared by hard ware and must be cleared by software. bit6: tf3l: timer 3 low byte overflow flag. set by hardware when the timer 3 low byte over flows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf3len is set and timer 3 interr upts are enabled. tf3l will set when the low byte overflow s regardless of the timer 3 mo de. this bit is not automat- ically cleared by hardware. bit5: tf3len: timer 3 low byte interrupt enable. this bit enables/disables timer 3 low byte in terrupts. if tf3len is set and timer 3 inter- rupts are enabled, an interrupt w ill be generated when the low byte of timer 3 overflows. this bit should be cleared when operating timer 3 in 16-bit mode. 0: timer 3 low byte interrupts disabled. 1: timer 3 low byte interrupts enabled. bit4: unused. read = 0b . write = don?t care. bit3: t3split: timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bit auto-reload timers. bit2: tr3: timer 3 run control. this bit enables/disables timer 3. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is always enabled in this mode. 0: timer 3 disabled. 1: timer 3 enabled. bit1: unused. read = 0b . write = don?t care. bit0: t3xclk: timer 3 external clock select. this bit selects the external cl ock source for timer 3. if timer 3 is in 8-bit mode, this bit selects the external o scillator clock source for both time r bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ck con) may still be used to select between the external clock and the system clock for either timer. 0: timer 3 external clock selection is the system clock divided by 12. 1: timer 3 external clock selection is the external clock divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf3h tf3l tf3len ? t3split tr3 ? t3xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x91
c8051f350/1/2/3 210 rev. 1.0 sfr definition 22.14. tmr3rll: timer 3 reload register low byte bits 7?0: tmr3rll: timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x92 sfr definition 22.15. tmr3rlh: timer 3 relo ad register high byte bits 7?0: tmr3rlh: timer 3 reload register high byte. the tmr3rlh holds the high byte of the reload value for timer 3. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x93 sfr definition 22.16. tmr3l: timer 3 low byte bits 7?0: tmr3l: timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x94 sfr definition 22.17. tmr3h timer 3 high byte bits 7?0: tmr3h: timer 3 high byte. in 16-bit mode, the tmr3h register contains t he high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x95
c8051f350/1/2/3 rev. 1.0 211 23. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. each capt ure/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled (see section ?18.1. priority crossbar decoder? on page 139 for details on configuring the crossbar). the counter/timer is driven by a programmable timebase that can select between six so urces: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, timer 0 overflow, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre - quency output, 8-bit pwm, or 16-bit pwm (each mode is described in section ?23.2. capture/compare modules? on page 213 ). the external oscillator clock option is i deal for real-time clock (rtc) functionality, allowing the pca to be clocked by a precision external oscill ator while the internal oscillator drives the sys - tem clock. the pca is configured and controlled th rough the system controller's special function regis - ters. the pca block diagram is shown in figure 23.1 important note: the pca module 2 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 23.3 for details. capture/compare module 1 capture/compare module 0 capture/compare module 2 / wdt cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 figure 23.1. pca block diagram
c8051f350/1/2/3 212 rev. 1.0 23.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counte r operation. the cps2?cps0 bits in the pca0md register select the timebase for the counter/timer as shown in ta b l e 23.1 . when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the in terrupt service routine, and must be cleared by soft - ware (note: pca0 interrupts must be globally enabled before cf interrupts are recognized. pca0 inter - rupts are globally enabled by setting the ea bit (ie.7) and the epca0 bit in eie1 to logic 1). clearing the cidl bit in the pca0md register a llows the pca to continue normal op eration while the cpu is in idle mode. table 23.1. pca timebase input options *note: external oscillator source divided by 8 is synchronized with the system clock. pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 figure 23.2. pca counter /timer block diagram cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 100system clock 1 0 1 external oscillator source divided by 8*
c8051f350/1/2/3 rev. 1.0 213 23.2. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. each module has special func tion registers (sfrs) asso ciated with it in the cip- 51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. ta b l e 23.2 summarizes the bit settings in the pca0cpmn registers used to select the pca capture/com - pare module?s operating modes. setting the eccfn bi t in a pca0cpmn register enables the module's ccfn interrupt. note: pca0 interrupts must be globally enabled before individual ccfn interrupts are rec - ognized. pca0 interrupts are globally enabled by se tting the ea bit and the epca0 bit to logic 1. see figure 23.3 for details on the pca interrupt configuration. table 23.2. pca0cpm register settings fo r pca capture/compare modules pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/ timer overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 2) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n figure 23.3. pca interrupt block diagram pwm16 ecom capp capn mat tog pwm eccf operation mode x x 10000x capture triggered by positive edge on cexn x x 01000x capture triggered by negative edge on cexn x x 11000x capture triggered by transition on cexn x 1 00100xsoftware timer x 1 00110xhigh speed output x 1 0 0 x 1 1 x frequency output 0 1 0 0 x 0 1 x 8-bit pulse width modulator 1 1 0 0 x 0 1 x 16-bit pulse width modulator x = don?t care
c8051f350/1/2/3 214 rev. 1.0 23.2.1. edge-triggered capture mode in this mode, a valid transition on the cexn pi n causes the pca to capture the value of the pca counter/timer and load it into the corresponding mo dule's 16-bit capture/compar e register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi - tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when th e cpu vectors to the interrupt service routine, and must be cleared by softwa re. if both cappn and capn n bits are set to logic 1, then the state of the port pin associated with cexn can be read directly to de termine whether a rising-edge or falling-edge caused the capture. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt 0x00x x figure 23.4. pca capture mode diagram note: the cexn input signal must re main high or low for at least 2 system clock cycles to be recognized by the hardware.
c8051f350/1/2/3 rev. 1.0 215 23.2.2. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hard ware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt figure 23.5. pca software timer mode diagram
c8051f350/1/2/3 216 rev. 1.0 23.2.3. high speed output mode in high speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln) setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high- speed output mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt figure 23.6. pca high speed output mode diagram
c8051f350/1/2/3 rev. 1.0 217 23.2.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out - put is toggled. the frequency of the square wave is then defined by equation 23.1 . f cexn f pca 2 pca 0 cphn ------------------- --------------------- - = note: a value of 0x00 in the pca0cphn re gister is equal to 256 for this equation. equation 23.1. square wave fr equency output where f pca is the frequency of the clock selected by the cps2?0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg - ister. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 23.7. pca frequency output mode
c8051f350/1/2/3 218 rev. 1.0 23.2.5. 8-bit pulse width modulator mode each module can be used independently to generate a pulse width modulated (pwm) output on its associ - ated cexn pin. the frequency of the output is depe ndent on the timebase for the pca counter/timer. the duty cycle of the pwm output signal is varied using the module's pca0cpln capture/compare register. when the value in the low byte of the pca counter/ti mer (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be se t. when the count value in pca0l overflows, the cexn output will be reset (see figure 23.8 ). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting t he ecomn and pwmn bits in the pca0cpmn register enables 8-bit pulse width modulator mode. the duty cycle for 8-bit pwm mode is given by equation 23.2 . important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. dutycycle 256 pca 0 cphn ? () 256 ------------------ ----------------- ---------------- = equation 23.2. 8-bit pwm duty cycle using equation 23.2, the largest duty cycle is 100% (pca0c phn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 23.8. pca 8-bi t pwm mode diagram
c8051f350/1/2/3 rev. 1.0 219 23.2.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. in this mode, the 16-bit capture/compare mod - ule defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the output on cexn is asserted high; when the counter over flows, cexn is asserted low. to output a varying duty cycle, new value wr ites should be synchroniz ed with pca ccfn match inter - rupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/co mpare register writes. the duty cycle for 16-bit pwm mode is given by equation 23.3 . important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0cphn sets ecomn to ?1?. dutycycle 65536 pca 0 cpn ? () 65536 ------------------ ------------------ ---------------- - = equation 23.3. 16-bit pwm duty cycle using equation 23.3, the largest duty cycle is 100% (pca0c pn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 23.9. pca 16-bit pwm mode
c8051f350/1/2/3 220 rev. 1.0 23.3. watchdog timer mode a programmable watchdog timer (wdt) function is avai lable through the pca module 2. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph2) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, modu le 2 operates as a watchdog timer (wdt). the mod - ule 2 high byte is compared to the pca counter high byte; the module 2 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. 23.3.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2?cps0) are frozen. ? pca idle control bi t (cidl) is frozen. ? module 2 is forced in to software timer mode. ? writes to the module 2 mode register (pca0cpm2) are disabled. while the wdt is enabled, writes to the cr bit will not change the pca counter state; the counter will run until the wdt is disabled. the pca co unter run co ntrol (cr) will read zero if the wdt is enabled but user software has not enabled the pca counter. if a ma tch occurs between pca0cph2 and pca0h while the wdt is enabled, a reset will be gener ated. to prevent a wdt reset, the wdt may be updated with a write of any value to pca0cph2. upon a pca0cph2 write, pca0h plus the offset held in pca0cpl2 is loaded into pca0cph2 (see figure 23.10 ). pca0h enable pca0l overflow reset pca0cpl2 8-bit adder pca0cph2 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph2 8-bit comparator figure 23.10. pca module 2 wi th watchdog timer enabled note that the 8-bit offset held in pca0cph2 is comp ared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the valu e of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 23.4 , where pca0l is the value of the pca0l register at the time of the update.
offset 256 pca 0 cpl 4 () () c8051f350/1/2/3 rev. 1.0 221 equation 23.4. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph2 and pca0h. software may force a wdt reset by writing a ?1? to the ccf2 flag (pca0cn.2) while the wdt is enabled. 23.3.2. watchdog timer usage to configure the wdt, perform the following tasks: ? disable the wdt by writing a ?0? to the wdte bit. ? select the desired pca clock s ource (with the cps2?cps0 bits). ? load pca0cpl2 with the desi red wdt update offset value. ? configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). ? enable the wdt by setting the wdte bit to ?1?. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any rese t. the pca0 counter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl2 defaults to 0x00. using equation 23.4 , this results in a wdt timeout interval of 256 system clock cycles. table 23.3 lists some example timeout intervals for typical sys - tem clocks. table 23.3. watchdog timer timeout intervals 1 notes: 1. assumes sysclk / 12 as the pc a clock source, and a pca0l value of 0x00 at the update time. 2. internal oscillator reset frequency. system clock (hz) pca0cpl2 timeout interval (ms) 24,500,000 255 32.1 24,500,000 128 16.2 24,500,000 32 4.1 18,432,000 255 42.7 18,432,000 128 21.5 18,432,000 32 5.5 11,059,200 255 71.1 11,059,200 128 35.8 11,059,200 32 9.2 3,062,500 2 255 257 3,062,500 2 128 129.5 3,062,500 2 32 33.1 32,000 255 24576 32,000 128 12384 32,000 32 3168
c8051f350/1/2/3 222 rev. 1.0 23.4. register descriptions for pca following are detailed descriptions of the special func tion registers related to the operation of the pca. sfr definition 23.1. pca0cn: pca control bit7: cf: pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) inte rrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bi t is not automatically cleared by hardware and must be cleared by software. bit6: cr: pca counter/ timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. bits5?3: unused. read = 000b, write = don't care. bit2: ccf2: pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf2 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit1: ccf1: pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf1 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit0: ccf0: pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf0 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. r/w r/w r r r r/w r/w r/w reset value cf cr ? ? ? ccf2 ccf1 ccf0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xd8
c8051f350/1/2/3 rev. 1.0 223 sfr definition 23.2. pca0md: pca mode bit7: cidl: pca counte r/timer idle control. specifies pca behavior wh en cpu is in idle mode. 0: pca continues to function normally while the system controller is in idle mode. 1: pca operation is suspended while the system controller is in idle mode. bit6: wdte: watchdog timer enable if this bit is set, pca module 2 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 2 enabled as watchdog timer. bit5: wdlck: watchdog timer lock this bit locks/unlocks the watchdog timer en able. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. bit4: unused. read = 0b, write = don't care. bits3?1: cps2?cps0: pca coun ter/timer pulse select. these bits select the timebase source for the pca counter . bit0: ecf: pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow interrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to ?1?, the pca0 md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled. r/w r/w r/w r r/w r/w r/w r/w reset value cidl wdte wdlck ? cps2 cps1 cps0 ecf 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xd9 cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external clock divided by 8* 1 1 0 reserved 1 1 1 reserved *note: external oscillator source divided by 8 is synchronized with the system clock.
c8051f350/1/2/3 224 rev. 1.0 sfr definition 23.3. pca0cpmn: pca capture/compare mode bit7: pwm16n: 16-bit pulse width modulation enable. this bit selects 16-bit mode when pulse width modulation mode is enabled (pwmn = 1). 0: 8-bit pwm selected. 1: 16-bit pwm selected. bit6: ecomn: comparator function enable. this bit enables/disables the comp arator function for pca module n. 0: disabled. 1: enabled. bit5: cappn: capture positi ve function enable. this bit enables/disables the positive edge capture for pca module n. 0: disabled. 1: enabled. bit4: capnn: capture negative function enable. this bit enables/disables the negative edge capture for pca module n. 0: disabled. 1: enabled. bit3: matn: match function enable. this bit enables/disables the match function for pca module n. when enabled, matches of the pca counter with a module's capture/comp are register cause the ccfn bit in pca0md register to be set to logic 1. 0: disabled. 1: enabled. bit2: togn: toggle function enable. this bit enables/disables the toggle function for pca module n. when enabled, matches of the pca counter with a module's capture/comp are register cause the logic level on the cexn pin to toggle. if the pwmn bit is also set to logic 1, the module operates in frequency output mode. 0: disabled. 1: enabled. bit1: pwmn: pulse width modulation mode enable. this bit enables/disables the pwm function for pca module n. when enabled, a pulse width modulated signal is output on the cexn pin. 8-bi t pwm is used if pwm16n is cleared; 16-bit mode is used if pwm16n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0: disabled. 1: enabled. bit0: eccfn: capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. r/w r/w r/w r/w r/w r/w r/w r/w reset value pwm16n ecomn cappn capnn matn togn pwmn eccfn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: pca0cpm0: 0xda, pca0cpm1: 0xdb, pca0cpm2: 0xdc
c8051f350/1/2/3 rev. 1.0 225 sfr definition 23.4. pca0l: pca counter/timer low byte bits 7?0: pca0l: pca co unter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf9 sfr definition 23.5. pca0h: pca counter /timer high byte bits 7?0: pca0h: pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: 0xfa
c8051f350/1/2/3 226 rev. 1.0 sfr definition 23.6. pca0cpln: pca capture module low byte bits7?0: pca0cpln: pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: pca0cpl0: 0xe9, pca0cpl1: 0xeb, pca0cpl2: 0xed sfr definition 23.7. pca0cphn: pca captur e module high byte bits7?0: pca0cphn: pca ca pture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: pca0cph0: 0xea, pca0cph1: 0xeb, pca0cph2: 0xee
c8051f350/1/2/3 rev. 1.0 227 24. c2 interface c8051f350/1/2/3 devices in clude an on-chip silicon la bs 2-wire (c2) debug inte rface to allow flash pro - gramming and in-system debugging with the production pa rt installed in the end a pplication. the c2 inter - face uses a clock signal (c2ck) and a bi-directiona l c2 data signal (c2d) to transfer information between the device and a host system. see the c2 interfac e specification for details on the c2 protocol. 24.1. c2 interface registers the following describes the c2 regi sters necessary to allow flash programming and in-system debugging with the production part installed through the c2 interface. all c2 registers are accessed through the c2 interface as described in th e c2 interface specification. c2 register definition 24.1. c2add: c2 address bits7?0: the c2add register is accessed via the c2 interface to select the ta rget data register for c2 data read and data write commands. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id regist er for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xb4 selects the c2 flash programming data register for data read/write instructions c2 register definition 24.2. deviceid: c2 device id this read-only register returns the 8-bit device id: 0x0b (c8051f350/1/2/3). reset value 00001011 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
c8051f350/1/2/3 228 rev. 1.0 c2 register definition 24.3. revid: c2 revision id this read-only register returns the 8-bit revision id. reset value variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c2 register definition 24.4. fpctl: c2 flash programming control bits7?0 fpctl: flash programming control register. this register is used to enable flash programmi ng via the c2 interface. to enable c2 flash programming, the following codes must be writte n in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset mu st be issued to resume normal operation. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c2 register definition 24.5. fpdat: c2 flash programming data bits7?0: fpdat: c2 flash programming data register. this register is used to pass flash comma nds, addresses, and data during c2 flash accesses. valid commands are listed below. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
c8051f350/1/2/3 rev. 1.0 229 24.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming functions may be performed. this is possible because c2 co mmunication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely ?b orrow? the c2ck (/rst) and c2d (p2.0) pins. in most applications, external resistors are required to isolat e c2 interface traffic from the user application. a typi - cal isolation configur ation is shown in figure 24.1 . c2d c2ck /reset (a) input (b) output (c) c2 interface master c8051fxxx figure 24.1. typical c2 pin sharing the configuration in figure 24.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the /rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application.
c8051f350/1/2/3 230 rev. 1.0 d ocument c hange l ist revision 0.4 to revision 1.0 ? removed preliminary tag and updated various specifications. ? updated package labeling and added "lead-free (rohs compliant)" in ta b l e 1.1, ?product selection guide,? on page 18 . ? adc chapter: added ta b l e 5.5 , ta b l e 5.6 , table 5.7 , ta b l e 5.8 , and ta b l e 5.9 on pages 63 ? 65 . ? temperature sensor chapter: added offset error and slope error specifications to ta b l e 8.1, ?temper - ature sensor electrical characteristics,? on page 77 . ? reset sources chapter: ta b l e 14.1, ?reset electrical characteristics,? on page 120 : added v dd ramp time and changed ?v dd por threshold? to ?v dd monitor threshold.? ? flash memory chapter: clarified descriptions of flash security features. ? oscillators chapter: clarified external crystal init ialization steps and added a specific 32.768 khz crys - tal example. ? oscillators chapter: clarified external capacitor example. ? port i/o chapter: figure 18.3 and figure 18.4 , crossbar priority decoder tables: changed pnskip[7:0] to pnskip[0:7] to match the port i/o order. ? smbus chapter: sfr definition 19.1 , smb0cf register: added a description of the behavior of timer 3 in split mode if smbtoe is set. ? pca chapter: updated watchdog timer timeout intervals in ta b l e 23.3 on page 221 . ? c2 chapter: removed references to ?boundary scans.?
c8051f350/1/2/3 rev. 1.0 231 n otes :
c8051f350/1/2/3 232 rev. 1.0 c ontact i nformation silicon laboratories inc. 4635 boston lane

▲Up To Search▲

Price & Availability of C8051F351

	To Download C8051F351 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .